A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. - Inhak Lee; Hanwool Jeong; Sangyeop Baeck; Siddharth Gupta 008; Changnam Park; Dongwook Seo; Jaeseung Choi 001; Jaeyoung Kim; Hoon Kim; Jungmyung Kang; Sunyung Jang; Daeyoung Moon; et al. (ISSCC, 2019)

5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. - Sangyeop Baeck; Inhak Lee; Hoyoung Tang; Dongwook Seo; Jaeseung Choi 001; Taejoong Song; Jongwook Kye (VLSI Circuits, 2021)

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. - Taejoong Song; Hakchul Jung; Giyoung Yang; Hoyoung Tang; Hayoung Kim; Dongwook Seo; Hoonki Kim; Woojin Rim; Sanghoon Baek; Sangyeop Baeck; Jonghoon Jung (CICC, 2022)

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications. - Keonhee Cho; Giseok Kim; Ji Sang Oh; Ki-Ryong Kim; Changsu Sim; Younmee Bae; Mijung Kim; Sangyeop Baeck; Taejoong Song; Seong-Ook Jung (VLSI Technology and Circuits, 2022)

4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits. - Inhak Lee; Dongwook Seo; Yunrong Li; Mijoung Kim; Sangyeop Baeck (VLSI Technology and Circuits, 2022)

A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V. - Gyuseong Kang; Hyunjin Shin; Hyuntaek Jung; Sunkyu Lee; Jaeseung Choi 001; Sangyeop Baeck; Hyunsung Jung; Daeshik Kim; Sohee Hwang; Shinhee Han; Yongsung Ji; Sei Seung Yoon (VLSI Technology and Circuits, 2023)

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. - Sekeon Kim; Keonhee Cho; Kyeongrim Baek; Hyunjun Kim; Younmee Bae; Mijung Kim; Dongwook Seo; Sangyeop Baeck; Sungjae Lee; Seong-Ook Jung (VLSI Technology and Circuits, 2023)

A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. - Jeongkyun Kim; Byungho Yook; Taemin Choi; Kyuwon Choi; Chanho Lee; Yunrong Li; Youngo Lee; Seok Yun; Changhoon Do; Hoyoung Tang; Inhak Lee; Dongwook Seo; et al. (VLSI Technology and Circuits, 2023)

A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1 Applications. - Gyuseong Kang; Hyunjin Shin; Sanggyeong Won; Dohui Kim; Kyuseong Kim; Soohoh Seol; Sunkyu Lee; Hangil Lee; Yeonho Jung; Jaechul Shim; Kiseok Suh; Sohee Hwang; et al. (VLSI Technology and Circuits, 2024)

A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology. - Jeongkyun Kim; Byungho Yook; Youngo Lee; Taemin Choi; Kyuwon Choi; Chanho Lee; Juchang Lee; Hyeongcheol Kim; Seok Yun; Changhoon Do; Minwoo Kwak; Mijoung Kim; et al. (IEEE J. Solid State Circuits, 2024)

SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes. - Keonhee Cho; Minjune Yeo; Seungjae Yei; Giseok Kim; Sangyeop Baeck; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2025)