A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology. - Ki-Tae Park; Ohsuk Kwon; Sangyong Yoon; Myung-Hoon Choi; In-Mo Kim; Bo-Geun Kim; Min-Seok Kim; Yoon-Hee Choi; Seung-Hwan Shin; Youngson Song; Joo-Yong Park; Jae-Eun Lee; et al. (ISSCC, 2011)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. - Seung-Hwan Shin; Dong-Kyo Shim; Jaeyong Jeong; Ohsuk Kwon; Sangyong Yoon; Myung-Hoon Choi; Tae-Young Kim; Hyun Wook Park; Hyun-Jun Yoon; Youngsun Song; Yoon-Hee Choi; Sang-Won Shim; et al. (VLSIC, 2012)

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. - Yong-Sung Cho; Il-Han Park; Sangyong Yoon; Nam-Hee Lee; Sang-Hyun Joo; Ki-Whan Song; Kihwan Choi; Jin-Man Han; Kyehyun Kyung; Young-Hyun Jun (IEEE J. Solid State Circuits, 2013)