Design space exploration of FPGA accelerators for convolutional neural networks. - Atul Rahman; Sangyun Oh; Jongeun Lee; Kiyoung Choi (DATE, 2017)

Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures. - Sangyun Oh; Hongsik Lee; Jongeun Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

RRNet: Repetition-Reduction Network for Energy Efficient Decoder of Depth Estimation. - Sangyun Oh; Hye-Jin S. Kim; Jongeun Lee; Junmo Kim 002 (CoRR, 2019)

Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling. - Yesung Kang; Yoonho Park; Sunghoon Kim; Eunji Kwon; Taeho Lim; Sangyun Oh; Mingyu Woo; Seokhyeong Kang (DATE, 2020)

RRNet: Repetition-Reduction Network for Energy Efficient Depth Estimation. - Sangyun Oh; Hye-Jin S. Kim; Jongeun Lee; Junmo Kim 002 (IEEE Access, 2020)

Automated Log-Scale Quantization for Low-Cost Deep Neural Networks. - Sangyun Oh; Hyeonuk Sim; Sugil Lee; Jongeun Lee (CVPR, 2021)

Non-uniform Step Size Quantization for Accurate Post-training Quantization. - Sangyun Oh; Hyeonuk Sim; Jounghyun Kim; Jongeun Lee (ECCV (11), 2022)

MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution. - Jooyeon Choi; Hyeonuk Sim; Sangyun Oh; Sugil Lee; Jongeun Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)