Effectiveness of heuristics measures for automatic test pattern generation. - Sanjay J. Patel; Janak H. Patel (DAC, 1986)

DECchip 21066: The Alpha AXP Chip for Cost-Focused Systems. - Dina L. McKinney; Daniel L. Leibholz; Mark B. Rosenbluth; James R. Mullens; Kwong-Tak A. Chui; Masooma Bhaiwala; Sanjay J. Patel; Christopher L. Houghton; Delvan A. Ramey (COMPCON, 1994)

Digital's DECchip 21066: The First Cost-focused Alpha AXP Chip - Dina L. McKinney; Masooma Bhaiwala; Kwong-Tak A. Chui; Christopher L. Houghton; James R. Mullens; Daniel L. Leibholz; Sanjay J. Patel; Delvan A. Ramey; Mark B. Rosenbluth (Digit. Tech. J., 1994)

Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. - Daniel H. Friendly; Sanjay J. Patel; Yale N. Patt (MICRO, 1997)

One Billion Transistors, One Uniprocessor, One Chip. - Yale N. Patt; Sanjay J. Patel; Marius Evers; Daniel H. Friendly; Jared Stark (Computer, 1997)

An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. - Marius Evers; Sanjay J. Patel; Robert S. Chappell; Yale N. Patt (ISCA, 1998)

Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. - Sanjay J. Patel; Marius Evers; Yale N. Patt (ISCA, 1998)

Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. - Daniel H. Friendly; Sanjay J. Patel; Yale N. Patt (MICRO, 1998)

Evaluation of Design Options for the Trace Cache Fetch Mechanism. - Sanjay J. Patel; Daniel H. Friendly; Yale N. Patt (IEEE Trans. Computers, 1999)

Trace cache design for wide-issue superscalar processors. - Sanjay J. Patel (1999)

Increasing the size of atomic instruction blocks using control flow assertions. - Sanjay J. Patel; Tony Tung; Satarupa Bose; Matthew M. Crum (MICRO, 2000)

Performance characterization of a hardware mechanism for dynamic optimization. - Brian Fahs; Satarupa Bose; Matthew M. Crum; Brian Slechta; Francesco Spadini; Tony Tung; Sanjay J. Patel; Steven S. Lumetta (MICRO, 2001)

rePLay: A Hardware Framework for Dynamic Optimization. - Sanjay J. Patel; Steven Lumetta (IEEE Trans. Computers, 2001)

Instruction fetch deferral using static slack. - Gregory A. Muthler; David Crowe; Sanjay J. Patel; Steven Lumetta (MICRO, 2002)

Y-Branches: When You Come to a Fork in the Road, Take It. - Nicholas J. Wang; Michael Fertig; Sanjay J. Patel (IEEE PACT, 2003)

Improving Quasi-Dynamic Schedules through Region Slip. - Francesco Spadini; Brian Fahs; Sanjay J. Patel; Steven S. Lumetta (CGO, 2003)

Dynamic Optimization of Micro-Operations. - Brian Slechta; David Crowe; Brian Fahs; Michael Fertig; Gregory A. Muthler; Justin Quek; Francesco Spadini; Sanjay J. Patel; Steven Lumetta (HPCA, 2003)

Characterization of essential dynamic instructions. - Steven Lumetta; Sanjay J. Patel (SIGMETRICS, 2003)

Introduction to computing systems - from bits and gates to C and beyond (2. ed.). - Yale N. Patt; Sanjay J. Patel (McGraw-Hill, 2004)

Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. - Nicholas J. Wang; Justin Quek; Todd M. Rafacz; Sanjay J. Patel (DSN, 2004)

Reducing the Scheduling Critical Cycle Using Wakeup Prediction. - Todd E. Ehrhart; Sanjay J. Patel (HPCA, 2004)

The Future of Computer Architecture Research: An Industrial Perspective. - Wen-mei W. Hwu; Sanjay J. Patel (HPCA, 2005)

Continuous Optimization. - Brian Fahs; Todd M. Rafacz; Sanjay J. Patel; Steven S. Lumetta (ISCA, 2005)

An Experimental Study of Soft Errors in Microprocessors. - Giacinto Paolo Saggese; Nicholas J. Wang; Zbigniew Kalbarczyk; Sanjay J. Patel; Ravishankar K. Iyer (IEEE Micro, 2005)

Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. - Ronald D. Barnes; John W. Sias; Erik M. Nystrom; Sanjay J. Patel; Nacho Navarro; Wen-mei W. Hwu (IEEE Trans. Computers, 2006)

ReStore: Symptom-Based Soft Error Detection in Microprocessors. - Nicholas J. Wang; Sanjay J. Patel (IEEE Trans. Dependable Secur. Comput., 2006)

Sequential Element Design With Built-In Soft Error Resilience. - Ming Zhang 017; Subhasish Mitra; T. M. Mak; Norbert Seifert; Nicholas J. Wang; Quan Shi; Kee Sup Kim; Naresh R. Shanbhag; Sanjay J. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Implicitly Parallel Programming Models for Thousand-Core Microprocessors. - Wen-mei W. Hwu; Shane Ryoo; Sain-Zee Ueng; John H. Kelm; Isaac Gelado; Sam S. Stone; Robert E. Kidd; Sara S. Baghsorkhi; Aqeel Mahesri; Stephanie C. Tsao; Nacho Navarro; Steven S. Lumetta; et al. (DAC, 2007)

Examining ACE analysis reliability estimates using fault-injection. - Nicholas J. Wang; Aqeel Mahesri; Sanjay J. Patel (ISCA, 2007)

ParallAX: an architecture for real-time physics. - Thomas Y. Yeh; Petros Faloutsos; Sanjay J. Patel; Glenn Reinman (ISCA, 2007)

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. - Thomas Y. Yeh; Petros Faloutsos; Milos D. Ercegovac; Sanjay J. Patel; Glenn Reinman (MICRO, 2007)

Hardware support for software controlled multithreading. - Aqeel Mahesri; Nicholas J. Wang; Sanjay J. Patel (SIGARCH Comput. Archit. News, 2007)

Tradeoffs in designing accelerator architectures for visual computing. - Aqeel Mahesri; Daniel R. Johnson; Neal Clayton Crago; Sanjay J. Patel (MICRO, 2008)

Guest Editors' Introduction: Accelerator Architectures. - Sanjay J. Patel; Wen-mei W. Hwu (IEEE Micro, 2008)

Optimization of tele-immersion codes. - Albert Sidelnik; I-Jui Sung; Wanmin Wu; María Jesús Garzarán; Wen-mei W. Hwu; Klara Nahrstedt; David A. Padua; Sanjay J. Patel (GPGPU, 2009)

Depth image-based rendering with low resolution depth. - Quang H. Nguyen; Minh N. Do; Sanjay J. Patel (ICIP, 2009)

Depth image-based rendering from multiple cameras with 3D propagation algorithm. - Quang H. Nguyen; Minh N. Do; Sanjay J. Patel (IMMERSCOM, 2009)

Rigel: an architecture and scalable programming interface for a 1000-core accelerator. - John H. Kelm; Daniel R. Johnson; Matthew R. Johnson 003; Neal Clayton Crago; William Tuohy; Aqeel Mahesri; Steven S. Lumetta; Matthew I. Frank; Sanjay J. Patel (ISCA, 2009)

Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design. - Omid Azizi; Aqeel Mahesri; Sanjay J. Patel; Mark Horowitz (SIGARCH Comput. Archit. News, 2009)

The parallelization of video processing. - Dennis J. Lin; Xiaohuang Huang; Quang H. Nguyen; Joshua Blackburn; Christopher I. Rodrigues; Thomas S. Huang; Minh N. Do; Sanjay J. Patel; Wen-Mei W. Hwu (IEEE Signal Process. Mag., 2009)

Fool me twice: Exploring and exploiting error tolerance in physics-based animation. - Thomas Y. Yeh; Glenn Reinman; Sanjay J. Patel; Petros Faloutsos (ACM Trans. Graph., 2009)

WAYPOINT: scaling coherence to thousand-core architectures. - John H. Kelm; Matthew R. Johnson 003; Steven S. Lumetta; Sanjay J. Patel (PACT, 2010)

An asymmetric distributed shared memory model for heterogeneous parallel systems. - Isaac Gelado; Javier Cabezas; Nacho Navarro; John E. Stone; Sanjay J. Patel; Wen-mei W. Hwu (ASPLOS, 2010)

An integrated framework for joint design space exploration of microarchitecture and circuits. - Omid Azizi; Aqeel Mahesri; John P. Stevenson; Sanjay J. Patel; Mark Horowitz (DATE, 2010)

GoldMine: Automatic assertion generation using data mining and static analysis. - Shobha Vasudevan; David Sheridan; Sanjay J. Patel; David Tcheng; William Tuohy; Daniel R. Johnson (DATE, 2010)

Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. - Omid Azizi; Aqeel Mahesri; Benjamin C. Lee; Sanjay J. Patel; Mark Horowitz (ISCA, 2010)

Cohesion: a hybrid memory model for accelerators. - John H. Kelm; Daniel R. Johnson; William Tuohy; Steven S. Lumetta; Sanjay J. Patel (ISCA, 2010)

Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture. - Stephen M. Kofsky; Daniel R. Johnson; John A. Stratton; Wen-mei W. Hwu; Sanjay J. Patel; Steven S. Lumetta (ISCA Workshops, 2010)

An adaptive performance modeling tool for GPU architectures. - Sara S. Baghsorkhi; Matthieu Delahaye; Sanjay J. Patel; William D. Gropp; Wen-mei W. Hwu (PPoPP, 2010)

A Task-Centric Memory Model for Scalable Accelerator Architectures. - John H. Kelm; Daniel R. Johnson; Steven S. Lumetta; Sanjay J. Patel; Matthew I. Frank (IEEE Micro, 2010)

Decoupled Architectures as a Low-Complexity Alternative to Out-of-order Execution. - Neal Clayton Crago; Sanjay J. Patel (PACT, 2011)

Accelerating aerial image simulation with GPU. - Hongbo Zhang 001; Tan Yan; Martin D. F. Wong; Sanjay J. Patel (ICCAD, 2011)

OUTRIDER: efficient memory latency tolerance with decoupled strands. - Neal Clayton Crago; Sanjay J. Patel (ISCA, 2011)

Rigel: A 1, 024-Core Single-Chip Accelerator Architecture. - Daniel R. Johnson; Matthew R. Johnson 003; John H. Kelm; William Tuohy; Steven S. Lumetta; Sanjay J. Patel (IEEE Micro, 2011)

Cohesion: An Adaptive Hybrid Memory Model for Accelerators. - John H. Kelm; Daniel R. Johnson; William Tuohy; Steven S. Lumetta; Sanjay J. Patel (IEEE Micro, 2011)

Immersive Visual Communication. - Minh N. Do; Quang H. Nguyen; Ha T. Nguyen; Daniel B. Kubacki; Sanjay J. Patel (IEEE Signal Process. Mag., 2011)

Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors. - Neal Clayton Crago; Omid Azizi; Steven S. Lumetta; Sanjay J. Patel (HPCA, 2013)

Accelerator Architectures A Ten-Year Retrospective. - Wen-Mei Hwu; Sanjay J. Patel (IEEE Micro, 2018)