FinFET SRAM design challenges. - David Burnett; Sanjay Parihar; Hema Ramamurthy; Sriram Balasubramanian (ICICDT, 2014)

SRAM Vmax stability considerations. - David Burnett; Sriram Balasubramanian; Vivek Joshi; Sanjay Parihar; Jack M. Higman; C. Weintraub (IRPS, 2015)

Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping. - Srinivas Jallepalli; Ram Mooraka; Sanjay Parihar; Earl Hunter; Elie Maalouf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling. - Srinivas Jallepalli; Ram Mooraka; Sanjay Parihar; Earl Hunter; Elie Maalouf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM. - Randy W. Mann; Meixiong Zhao; Sanjay Parihar; Qun Gao; Ankur Arya; Carl Radens; Shesh Mani Pandey; Joseph Versaggi; Jack M. Higman; Rick Carter (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An Energy-Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network. - Gobinda Saha; Zhewei Jiang; Sanjay Parihar; Xi Cao; Jack M. Higman; Muhammed Ahosan Ul Karim (IEEE Access, 2020)

Bias-Dependent Variation in FinFET SRAM. - Randy W. Mann; Meixiong Zhao; Oh Sung Kwon; Xi Cao; Sanjay Parihar; Muhammed Ahosan Ul Karim; Jack M. Higman; Joseph Versaggi; Rick Carter (IEEE Trans. Very Large Scale Integr. Syst., 2020)

An In-Memory-Computing Binary Neural Network Architecture With In-Memory Batch Normalization. - Prathamesh Prashant Rege; Ming Yin; Sanjay Parihar; Joseph Versaggi; Shashank S. Nemawarkar (IEEE Access, 2024)