Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs. - Sitaram Yadavalli; Sanjay Sengupta (VLSI Design, 1998)

Test challenges in nanometer technologies. - Sandip Kundu; Sanjay Sengupta; Rajesh Galivanche (ETW, 2000)

Test Challenges in Nanometer Technologies. - Sandip Kundu; Sujit T. Zachariah; Sanjay Sengupta; Rajesh Galivanche (J. Electron. Test., 2001)

Test Strategies for Nanometer Technologies. - Sanjay Sengupta (ITC, 2004)

CONCAT: CONflict Driven Learning in ATPG for Industrial designs. - Surendra Bommu; Kameshwar Chandrasekar; Rahul Kundu; Sanjay Sengupta (ITC, 2008)

Low Coverage Analysis using dynamic un-testability debug in ATPG. - Kameshwar Chandrasekar; Surendra Bommu; Sanjay Sengupta (VTS, 2011)

A scan pattern debugger for partial scan industrial designs. - Kameshwar Chandrasekar; Supratik K. Misra; Sanjay Sengupta; Michael S. Hsiao (DATE, 2012)

A Cube-Aware Compaction Method for Scan ATPG. - Sharada Jha; Kameshwar Chandrasekar; Weixin Wu; Ramesh Sharma; Sanjay Sengupta; Sudhakar M. Reddy (VLSID, 2014)