Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. - Thomas M. Conte; Sanjeev Banerjia; Sergei Y. Larin; Kishore N. Menezes; Sumedh W. Sathaye (MICRO, 1996)

A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. - Thomas M. Conte; Sumedh W. Sathaye; Sanjeev Banerjia (MICRO, 1996)

Treegion Scheduling for Highly Parallel Processors. - Sanjeev Banerjia; William A. Havanki; Thomas M. Conte (Euro-Par, 1997)

A Fast Interrupt Handling Scheme for VLIW Processors. - Emre Özer 001; Sumedh W. Sathaye; Kishore N. Menezes; Sanjeev Banerjia; Matthew D. Jennings; Thomas M. Conte (IEEE PACT, 1998)

Treegion Scheduling for Wide Issue Processors. - William A. Havanki; Sanjeev Banerjia; Thomas M. Conte (HPCA, 1998)

Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. - Emre Özer 001; Sanjeev Banerjia; Thomas M. Conte (MICRO, 1998)

MPS: Miss-Path Scheduling for Multiple-Issue Processors. - Sanjeev Banerjia; Sumedh W. Sathaye; Kishore N. Menezes; Thomas M. Conte (IEEE Trans. Computers, 1998)

Dynamo: a transparent dynamic optimization system. - Vasanth Bala; Evelyn Duesterwald; Sanjeev Banerjia (PLDI, 2000)