A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. - Samiran Halder; Swapna Banerjee; Arindrajit Ghosh; Ravi Sankar Prasad; Anirban Chatterjee; Sanjoy Kumar Dey (VLSI Design, 2005)

An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. - Sanjoy Kumar Dey; Swapna Banerjee (VLSI Design, 2006)

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. - Santanu Sarkar 002; Ravi Sankar Prasad; Sanjoy Kumar Dey; Vinay Belde; Swapna Banerjee (ISCAS, 2008)

Modelling the Effect of Output-Dependent Integrator Gain on the Unadjusted Error of Inverter Based 1stOrder $ Sigma Delta$ ADC. - Ashish Joshi; Tapas Nandy; Aashish T. R; Mayank Devam; Sanjoy Kumar Dey (APCCAS, 2023)

Large Network of Wide- Range Analog Voltage Observers for Debug & Testability. - Tapas Nandy; Ashish Joshi; Sanjoy Kumar Dey (APCCAS, 2023)

Energy efficiency optimization in Strong-Arm latch-based dynamic comparator by capacitor distribution. - Sanjoy Kumar Dey; Mukul Sarkar; Shouribrata Chatterjee (ISCAS, 2023)

A low-power resistive tail dynamic comparator with self-shut mechanism. - Sanjoy Kumar Dey; Mukul Sarkar; Shouribrata Chatterjee (VLSID, 2023)

Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits. - Saurabh Goyal; Sanjay Kumar Wadhwa; Divya Tripathi; Gaurav Agrawal; Krishna Thakur; Deependra Kumar Jain; Alvin Leng Sun Loke; Atul Kumar; Manish Kumar Upadhyay; Bhawna; Sanjoy Kumar Dey (VLSID, 2023)

A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications. - Sanjoy Kumar Dey; Arun Kumar Barman; Pawan Sehgal; Mukul Sarkar; Shouribrata Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2025)