An Improved Lower Bound to the Number of Neighbors Required for the Asymptotic Connectivity of Ad Hoc Networks - Sanquan Song; Dennis Goeckel; Donald F. Towsley (CoRR, 2005)

Collaboration Improves the Connectivity of Wireless Networks. - Sanquan Song; Dennis Goeckel; Donald F. Towsley (INFOCOM, 2006)

A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links. - Sanquan Song; Vladimir Stojanovic (IEEE J. Solid State Circuits, 2011)

FSE for high-speed links. - Sanquan Song (2011)

An input pole tuned switching equalization scheme for high-speed serial links. - Sanquan Song; Jian Xu; Fengxiang Cai; Xin Ma; Zibing Yang; Matthew Becker; Larry Tate; Byungsub Kim; Samuel Palermo; William J. Bowhill (MWSCAS, 2015)

23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays. - Mohammad Hekmat; Sanquan Song; Nancy Jaffari; Sabarish Sankaranarayanan; Chaofeng Huang; Minghui Han; Gaurav Malhotra; Jalil Kamali; Amir Amirkhany; Wei Xiong (ISSCC, 2016)

An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines. - Jaeyoung Seo; Minsoo Choi 002; Sanquan Song; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. - Sudhir S. Kudva; Sanquan Song; John W. Poulton; John M. Wilson 002; Wenxu Zhao; C. Thomas Gray (CICC, 2018)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. - Xi Chen 033; Sanquan Song; John Poulton; Nikola Nedovic; Brian Zimmer; Stephen G. Tell; C. Thomas Gray (CICC, 2019)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. - Hao Chen 059; Walker J. Turner; Sanquan Song; Keren Zhu 001; George F. Kokai; Brian Zimmer; C. Thomas Gray; Brucek Khailany; David Z. Pan; Haoxing Ren (ISPD, 2022)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. - Sanquan Song; Stephen G. Tell; Brian Zimmer; Sudhir S. Kudva; Nikola Nedovic; C. Thomas Gray (VLSI Technology and Circuits, 2022)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. - Walker J. Turner; John W. Poulton; Yoshinori Nishi; Xi Chen 033; Brian Zimmer; Sanquan Song; John M. Wilson 002; William J. Dally; C. Thomas Gray (CICC, 2024)

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. - Sudhir S. Kudva; Mahmut Ersin Sinangil; Stephen G. Tell; Nikola Nedovic; Sanquan Song; Brian Zimmer; C. Thomas Gray (ISSCC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)

17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process. - Nandish Mehta; Stephen G. Tell; Sanquan Song; Sudhir S. Kudva; Brian Zimmer; Mahmut E. Sinangil; C. Thomas Gray (ISSCC, 2025)