A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI. - Sanroku Tsukamoto; I. Dedic; Toshiaki Endo; K. y. Kikuta; K. Goto; O. Kobayashi (IEEE J. Solid State Circuits, 1996)

A CMOS 6-b, 400-MSample/s ADC with error correction. - Sanroku Tsukamoto; William G. Schofield; Toshiaki Endo (IEEE J. Solid State Circuits, 1998)

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing. - Masato Yoshioka; Masahiro Kudo; Toshihiko Mori; Sanroku Tsukamoto (ISSCC, 2007)

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. - Sanroku Tsukamoto; Shen-Iuan Liu; Stefan Heinen; Roland Thewes; Jri Lee (IEEE J. Solid State Circuits, 2008)

A 1 GHz CMOS comparator with dynamic offset control technique. - Xiaolei Zhu 002; Sanroku Tsukamoto; Tadahiro Kuroda (ASP-DAC, 2009)

A 6b 3GS/s flash ADC with background calibration. - Masashi Kijima; Kenji Ito; Kuniyoshi Kamei; Sanroku Tsukamoto (CICC, 2009)

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration. - Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Sanroku Tsukamoto (ISSCC, 2010)

A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS. - Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. - Yanfei Chen; Xiaolei Zhu 002; Hirotaka Tamura; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Junji Ogawa; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. - Xiaolei Zhu 002; Yanfei Chen; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Hirotaka Tamura; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration. - Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Sanroku Tsukamoto (IEEE Trans. Biomed. Circuits Syst., 2010)

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS. - Takumi Danjo; Masato Yoshioka; Masayuki Isogai; Masanori Hoshino; Sanroku Tsukamoto (VLSI-DAT, 2012)

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. - Xiaolei Zhu 002; Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda (VLSI-DAT, 2012)

A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration. - Xiaolei Zhu 002; Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2012)

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (ISSCC, 2013)

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (IEEE J. Solid State Circuits, 2013)

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. - Kentaro Yoshioka; Ryo Saito; Takumi Danjo; Sanroku Tsukamoto; Hiroki Ishikuro (VLSIC, 2014)

A 7-bit 1-GS/s Flash ADC with Background Calibration. - Sanroku Tsukamoto; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2014)

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. - Takumi Danjo; Masato Yoshioka; Masayuki Isogai; Masanori Hoshino; Sanroku Tsukamoto (IEEE J. Solid State Circuits, 2014)

Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. - Kentaro Yoshioka; Ryo Saito; Takumi Danjo; Sanroku Tsukamoto; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2015)

Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. - Satoshi Matsubara; Hirotaka Tamura; Motomu Takatsu; Danny Yoo; Behraz Vatankhahghadim; Hironobu Yamasaki; Toshiyuki Miyazawa; Sanroku Tsukamoto; Yasuhiro Watanabe; Kazuya Takemoto; Ali Sheikholeslami (CISIS, 2017)

Advances in Analog-to-Digital Converters over the Last Decade. - Sanroku Tsukamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)