Mesh-of-tree deterministic routing for network-on-chip architecture. - Santanu Kundu; Santanu Chattopadhyay (ACM Great Lakes Symposium on VLSI, 2008)

Mesh-of-Tree Based Scalable Network-on-Chip Architecture. - Santanu Kundu; Radha Purnima Dasari; Santanu Chattopadhyay; Kanchan Manna (ICIIS, 2008)

Network-on-chip architecture design based on mesh-of-tree deterministic routing topology. - Santanu Kundu; Santanu Chattopadhyay (Int. J. High Perform. Syst. Archit., 2008)

A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic. - Santanu Kundu; Kanchan Manna; Shobhit Gupta; Kundan Kumar; Ritesh Parikh; Santanu Chattopadhyay (ARTCom, 2009)

Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits. - Santanu Kundu; Santanu Chattopadhyay (ISVLSI, 2011)

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router. - Santanu Kundu; Soumya J.; Santanu Chattopadhyay (Microprocess. Microsystems, 2012)

Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths. - Tuhin Subhra Chakraborty; Santanu Kundu; Deepak Agrawal; Sanjay Tanaji Shinde; Jacob Mathews; Rekha K. James (ACM Great Lakes Symposium on VLSI, 2016)

MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence. - Santanu Kundu; Manoranjan Prasad; Sashank Nishad; Sandeep Nachireddy; Harikrishnan K (VLSID, 2022)

MLTDRC: Machine Learning Driven Faster Timing Design Rule Check Convergence. - Santanu Kundu; Chetan Suryakant Padharia; Ravi Sankar Kerla (VLSID, 2023)

MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy. - Sashank Nishad; Santanu Kundu; Nicolas Richaud; S. Mallikarjun; Manoranjan Prasad; Lennart Renker (VLSID, 2024)

Unlocking the Power of Machine Learning for Faster PCB Package and Board PDN Convergence. - Manoranjan Prasad; Santanu Kundu; Lennart Renker; Rakesh Ranjan (VLSID, 2024)