A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. - Santanu Sarkar 002; Arindrajit Ghosh; Swapna Banerjee (APCCAS, 2006)

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. - Santanu Sarkar 002; Ravi Sankar Prasad; Sanjoy Kumar Dey; Vinay Belde; Swapna Banerjee (ISCAS, 2008)

An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. - Santanu Sarkar 002; Swapna Banerjee (ISVLSI, 2009)

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters. - Santanu Sarkar 002; Swapna Banerjee (Microelectron. J., 2014)

A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. - Santanu Sarkar 002; Swapna Banerjee (ISVLSI, 2015)

A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters. - Smrutilekha Samanta; Santanu Sarkar 002 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An 8-bit 1 MS/s Low-Power SAR ADC with an Enhanced EPC for Implantable Medical Devices. - Deepika Kumaradasan; Sougata Kumar Kar; Santanu Sarkar 002 (ISVLSI, 2024)

A 13-Bit Resolution High Performance Time Domain Comparator Using Intermediate Buffer Based VCO. - Mirza Amanullah Baig; Santanu Sarkar 002 (TENCON, 2024)

A Low-Power 10-bit SAR ADC with an Integrated CDAC and C-MOSCAP DAC for Implantable Pacemakers. - Deepika Kumaradasan; Sougata Kumar Kar; Santanu Sarkar 002 (VDAT, 2024)