A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. - Yohan Frans; Mohamed Elzeftawi; Hiva Hedayati; Jay Im; Vassili Kireev; Toan Pham; Jaewook Shin; Parag Upadhyaya; Lei Zhou; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (VLSI Circuits, 2016)

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. - Yohan Frans; Jaewook Shin; Lei Zhou; Parag Upadhyaya; Jay Im; Vassili Kireev; Mohamed Elzeftawi; Hiva Hedayati; Toan Pham; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (IEEE J. Solid State Circuits, 2017)

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. - Kevin Zheng; Yohan Frans; Sai Lalith Ambatipudi; Santiago Asuncion; Hari Teja Reddy; Ken Chang; Boris Murmann (VLSI Circuits, 2018)

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. - Mayank Raj; Chuan Xie; Ade Bekele; Adam Chou; Wenfeng Zhang; Ying Cao 010; Jae Wook Kim; Nakul Narang; Hongyuan Zhao; Yipeng Wang 003; Kee Hian Tan; Winson Lin; et al. (ISSCC, 2023)