An area optimized reconfigurable encryptor for AES-Rijndael. - Monjur Alam; Sonai Ray; Debdeep Mukhopadhyay; Santosh Ghosh; Dipanwita Roy Chowdhury; Indranil Sengupta 001 (DATE, 2007)

A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography. - Santosh Ghosh; Monjur Alam; Indranil Sengupta 001; Dipanwita Roy Chowdhury (DSD, 2007)

A Speed-Area Optimization of Full Search Block Matching Hardware with Applications in High-Definition TVs (HDTV). - Avishek Saha; Santosh Ghosh (HiPC, 2007)

Speed-area optimized FPGA implementation for Full Search Block Matching. - Santosh Ghosh; Avishek Saha (ICCD, 2007)

Toward Memory-efficient Design of Video Encoders for Multimedia Applications. - Avishek Saha; Santosh Ghosh; Shamik Sural; Jayanta Mukherjee 001 (ISVLSI, 2007)

A GF(p) elliptic curve group operator resistant against side channel attacks. - Santosh Ghosh; Monjur Alam; Dipanwita Roy Chowdhury; Indranil Sengupta 001 (ACM Great Lakes Symposium on VLSI, 2008)

Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm. - Monjur Alam; Santosh Ghosh; Dipanwita Roy Chowdhury; Indranil Sengupta 001 (VLSI Design, 2008)

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks. - Santosh Ghosh; Monjur Alam; Dipanwita Roy Chowdhury; Indranil Sengupta 001 (Comput. Electr. Eng., 2009)

Effect of glitches against masked AES S-box implementation and countermeasure. - Monjur Alam; Santosh Ghosh; M. J. Mohan; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury; Indranil Sengupta 001 (IET Inf. Secur., 2009)

High speed Fp multipliers and adders on FPGA platform. - Santosh Ghosh; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (DASIP, 2010)

High Speed Flexible Pairing Cryptoprocessor on FPGA Platform. - Santosh Ghosh; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (Pairing, 2010)

High Speed Cryptoprocessor for η T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields. - Santosh Ghosh; Dipanwita Roy Chowdhury; Abhijit Das 004 (CHES, 2011)

Security of Prime Field Pairing Cryptoprocessor against Differential Power Attack. - Santosh Ghosh; Dipanwita Roy Chowdhury (InfoSecHiComNet, 2011)

Design and Analysis of Pairing Based Cryptographic Hardware for Prime Fields. - Santosh Ghosh (ISVLSI, 2011)

Security of Prime Field Pairing Cryptoprocessor Against Differential Power Attack. - Santosh Ghosh; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (IACR Cryptol. ePrint Arch., 2011)

Fault Attack, Countermeasures on Pairing Based Cryptography. - Santosh Ghosh; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (Int. J. Netw. Secur., 2011)

Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit. - Santosh Ghosh; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A Speed Area Optimized Embedded Co-processor for McEliece Cryptosystem. - Santosh Ghosh; Jeroen Delvaux; Leif Uhsadel; Ingrid Verbauwhede (ASAP, 2012)

Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor. - Baris Ege; Amitabh Das; Santosh Ghosh; Ingrid Verbauwhede (DSD, 2012)

Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform. - Santosh Ghosh; Ingrid Verbauwhede; Dipanwita Roy Chowdhury (Pairing, 2012)

Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks. - Arpan Mondal; Santosh Ghosh; Abhijit Das 004; Dipanwita Roy Chowdhury (VDAT, 2012)

Scan attacks on side-channel and fault attack resistant public-key implementations. - Jean DaRolt; Amitabh Das; Santosh Ghosh; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (J. Cryptogr. Eng., 2012)

Secure JTAG Implementation Using Schnorr Protocol. - Amitabh Das; Jean DaRolt; Santosh Ghosh; Stefaan Seys; Sophie Dupuis; Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Ingrid Verbauwhede (J. Electron. Test., 2013)

First-order DPA Vulnerability of Rijndael: Security and Area-delay Optimization Trade-off. - Monjur Alam; Santosh Ghosh; Dipanwita Roy Chowdhury; Indranil Sengupta 001 (Int. J. Netw. Secur., 2013)

Security Analysis of Industrial Test Compression Schemes. - Amitabh Das; Baris Ege; Santosh Ghosh; Lejla Batina; Ingrid Verbauwhede (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform. - Santosh Ghosh; Debdeep Mukhopadhyay; Dipanwita Roy Chowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2013)

On the implementation of mceliece with CCA2 indeterminacy by SHA-3. - Santosh Ghosh (ISCAS, 2014)

Indian thermal power plant challenges and remedies via application of modified data envelopment analysis. - Vinod Kumar Yadav; Niranjan Kumar; Santosh Ghosh; Kanwardeep Singh (Int. Trans. Oper. Res., 2014)

BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor. - Santosh Ghosh; Ingrid Verbauwhede (IEEE Trans. Computers, 2014)

On the Implementation of Unified Arithmetic on Binary Huff Curves. - Santosh Ghosh; Amit Kumar; Amitabh Das; Ingrid Verbauwhede (IACR Cryptol. ePrint Arch., 2015)

Parsimonious design strategy for linear layers with high diffusion in block ciphers. - Sikhar Patranabis; Debapriya Basu Roy; Yash Shrivastava; Debdeep Mukhopadhyay; Santosh Ghosh (HOST, 2016)

Shuffling across rounds: A lightweight strategy to counter side-channel attacks. - Sikhar Patranabis; Debapriya Basu Roy; Praveen Kumar Vadnala; Debdeep Mukhopadhyay; Santosh Ghosh (ICCD, 2016)

High efficiency power side-channel attack immunity using noise injection in attenuated signature domain. - Debayan Das; Shovan Maity; Saad Bin Nasir; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (HOST, 2017)

Lightweight Block Cipher Circuits for Automotive and IoT Sensor Devices. - Santosh Ghosh; Rafael Misoczki; Li Zhao 002; Manoj R. Sastry (HASP@ISCA, 2017)

A first look at performance of TV streaming sticks. - Ayon Chakraborty; Arani Bhattacharya; Santosh Ghosh; Samir R. Das (Sarnoff Symposium, 2017)

An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security. - Rajat Sadhukhan; Sikhar Patranabis; Ashrujit Ghoshal; Debdeep Mukhopadhyay; Vishal Saraswat; Santosh Ghosh (J. Hardw. Syst. Secur., 2017)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator. - Monodeep Kar; Arvind Singh; Sanu Mathew; Santosh Ghosh; Anand Rajan; Vivek De; Raheem A. Beyah; Saibal Mukhopadhyay (CoRR, 2018)

Ground-up Root-cause Analysis guided Low-Overhead Generic Countermeasure for Electro-Magnetic Side-Channel Attack. - Debayan Das; Mayukh Nath; Baibhab Chatterjee; Santosh Ghosh; Shreyas Sen (IACR Cryptol. ePrint Arch., 2018)

ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity. - Debayan Das; Shovan Maity; Saad Bin Nasir; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis. - Debayan Das; Mayukh Nath; Baibhab Chatterjee; Santosh Ghosh; Shreyas Sen (HOST, 2019)

SCNIFFER: Low-Cost, Automated, EfficientElectromagnetic Side-Channel Sniffing. - Josef Danial; Debayan Das; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (CoRR, 2019)

Intelligent IoT Motes: Preventing Their Abuse at the Weakest Entry Point. - Santosh Ghosh; Rafael Misoczki; Manoj R. Sastry (IEEE Des. Test, 2019)

X-DeepSCA: Cross-Device Deep Learning Side Channel Attack. - Debayan Das; Anupam Golder; Josef Danial; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IACR Cryptol. ePrint Arch., 2019)

Lightweight Post-Quantum-Secure Digital Signature Approach for IoT Motes. - Santosh Ghosh; Rafael Misoczki; Manoj R. Sastry (IACR Cryptol. ePrint Arch., 2019)

Anonymous Attestation for IoT. - Santosh Ghosh; Andrew H. Reinders; Rafael Misoczki; Manoj R. Sastry (IACR Cryptol. ePrint Arch., 2019)

Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications. - Sikhar Patranabis; Debapriya Basu Roy; Anirban Chakraborty 003; Naveen Nagar; Astikey Singh; Debdeep Mukhopadhyay; Santosh Ghosh (J. Hardw. Syst. Secur., 2019)

Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack. - Anupam Golder; Debayan Das; Josef Danial; Santosh Ghosh; Shreyas Sen; Arijit Raychowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS. - Debayan Das; Josef Danial; Anupam Golder; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (CICC, 2020)

HCC: 100 Gbps AES-GCM Encrypted Inline DMA Transfers Between SGX Enclave and FPGA Accelerator. - Luis S. Kida; Soham Jayesh Desai; Alpa Trivedi; Reshma Lal; Vincent Scarlata; Santosh Ghosh (ICICS, 2020)

K-Cipher: A Low Latency, Bit Length Parameterizable Cipher. - Michael E. Kounavis; Sergej Deutsch; Santosh Ghosh; David Durham (ISCC, 2020)

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (ISSCC, 2020)

Killing EM Side-Channel Leakage at its Source. - Debayan Das; Mayukh Nath; Santosh Ghosh; Shreyas Sen (MWSCAS, 2020)

Virtual Consensus in Delos. - Mahesh Balakrishnan 001; Jason Flinn; Chen Shen; Mihir Dharamshi; Ahmed Jafri; Xiao Shi; Santosh Ghosh; Hazem Hassan; Aaryaman Sagar; Rhed Shi; Jingming Liu; Filip Gruszczynski; et al. (OSDI, 2020)

SCNIFFER: Low-Cost, Automated, Efficient Electromagnetic Side-Channel Sniffing. - Josef Danial; Debayan Das; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IEEE Access, 2020)

Gimli Encryption in 715.9 psec. - Santosh Ghosh; Michael E. Kounavis; Sergej Deutsch (IACR Cryptol. ePrint Arch., 2020)

A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device. - Santosh Ghosh; Luis S. Kida; Soham Jayesh Desai; Reshma Lal (IACR Cryptol. ePrint Arch., 2020)

Κ-Cipher: A Low Latency, Bit Length Parameterizable Cipher. - Michael E. Kounavis; Sergej Deutsch; Santosh Ghosh; David Durham (IACR Cryptol. ePrint Arch., 2020)

Efficient BIKE Hardware Design with Constant-Time Decoder. - Andrew H. Reinders; Rafael Misoczki; Santosh Ghosh; Manoj R. Sastry (IACR Cryptol. ePrint Arch., 2020)

Towards efficient and automated side-channel evaluations at design time. - Danilo Sijacic; Josep Balasch; Bohan Yang 001; Santosh Ghosh; Ingrid Verbauwhede (J. Cryptogr. Eng., 2020)

Constraints for effective distribution network expansion planning: an ample review. - Mandhir Kumar Verma; Vivekananda Mukherjee; Vinod Kumar Yadav; Santosh Ghosh (Int. J. Syst. Assur. Eng. Manag., 2020)

Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing. - Dong-Hyun Seo; Mayukh Nath; Debayan Das; Santosh Ghosh; Shreyas Sen (DATE, 2021)

PG-CAS: Patterned-Ground Co-Planar Capacitive Asymmetry Sensing for mm-Range EM Side-Channel Attack Probe Detection. - Dong-Hyun Seo; Mayukh Nath; Debayan Das; Baibhab Chatterjee; Santosh Ghosh; Shreyas Sen (ISCAS, 2021)

36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control. - Archisman Ghosh; Debayan Das; Josef Danial; Vivek De; Santosh Ghosh; Shreyas Sen (ISSCC, 2021)

Cryptographic Capability Computing. - Michael LeMay; Joydeep Rakshit; Sergej Deutsch; David M. Durham; Santosh Ghosh; Anant Nori; Jayesh Gaur; Andrew Weiler; Salmin Sultana; Karanvir Grewal; Sreenivas Subramoney (MICRO, 2021)

Log-structured Protocols in Delos. - Mahesh Balakrishnan 001; Chen Shen; Ahmed Jafri; Suyog Mapara; David Geraghty; Jason Flinn; Vidhya Venkat; Ivailo Nedelchev; Santosh Ghosh; Mihir Dharamshi; Jingming Liu; Filip Gruszczynski; et al. (SOSP, 2021)

EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures. - Debayan Das; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IEEE Des. Test, 2021)

Where Star Wars Meets Star Trek: SABER and Dilithium on the Same Polynomial Multiplier. - Andrea Basso 001; Furkan Aydin; Daniel Dinu; Joseph Friel; Avinash Varna 001; Manoj R. Sastry; Santosh Ghosh (IACR Cryptol. ePrint Arch., 2021)

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish K. Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (IEEE J. Solid State Circuits, 2021)

A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator. - Archisman Ghosh; Jose Maria Bermudo Mera; Angshuman Karmakar; Debayan Das; Santosh Ghosh; Ingrid Verbauwhede; Shreyas Sen (CICC, 2022)

A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256. - Archisman Ghosh; Dong-Hyun Seo; Debayan Das; Santosh Ghosh; Shreyas Sen (CICC, 2022)

EM SCA & FI Self-Awareness and Resilience with Single On-chip Loop & ML Classifiers. - Archisman Ghosh; Debayan Das; Santosh Ghosh; Shreyas Sen (DATE, 2022)

A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator. - Archisman Ghosh; Jose Maria Bermudo Mera; Angshuman Karmakar; Debayan Das; Santosh Ghosh; Ingrid Verbauwhede; Shreyas Sen (CoRR, 2022)

Optimization for SPHINCS+ using Intel Secure Hash Algorithm Extensions. - Thomas Hanson; Qian Wang; Santosh Ghosh; Fernando Virdia; Anne Reinders; Manoj R. Sastry (IACR Cryptol. ePrint Arch., 2022)

EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures. - Josef Danial; Debayan Das; Anupam Golder; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (ACM J. Emerg. Technol. Comput. Syst., 2022)

Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation. - Archisman Ghosh; Debayan Das; Josef Danial; Vivek De; Santosh Ghosh; Shreyas Sen (IEEE J. Solid State Circuits, 2022)

EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation. - Debayan Das; Mayukh Nath; Baibhab Chatterjee; Raghavan Kumar; Xiaosen Liu; Harish Krishnamurthy; Manoj R. Sastry; Sanu Mathew; Santosh Ghosh; Shreyas Sen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware. - Jan Richter-Brockmann; Ming-Shing Chen; Santosh Ghosh; Tim Güneysu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits. - Archisman Ghosh; Md. Abdur Rahman; Debayan Das; Santosh Ghosh; Shreyas Sen (CICC, 2023)

Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK. - Anupam Golder; Debayan Das; Santosh Ghosh; Avinash Varna 001; Majid Sabbagh; Sayak Ray; Rana Elnaggar; Joseph Friel; Daniel Dinu; Jason M. Fung (DAC, 2023)

A 334μW 0.158mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Authors Version. - Archisman Ghosh; Jose Maria Bermudo Mera; Angshuman Karmakar; Debayan Das; Santosh Ghosh; Ingrid Verbauwhede; Shreyas Sen (CoRR, 2023)

Introducing two Low-Latency Cipher Families: Sonic and SuperSonic. - Yanis Belkheyar; Joan Daemen; Christoph Dobraunig; Santosh Ghosh; Shahram Rasoolzadeh (IACR Cryptol. ePrint Arch., 2023)

A 334ÂµW 0.158mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Extended Version. - Archisman Ghosh; Jose Maria Bermudo Mera; Angshuman Karmakar; Debayan Das; Santosh Ghosh; Ingrid Verbauwhede; Shreyas Sen (IACR Cryptol. ePrint Arch., 2023)

A 334 μW 0.158 mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom-Cook Multiplication. - Archisman Ghosh; Jose Maria Bermudo Mera; Angshuman Karmakar; Debayan Das; Santosh Ghosh; Ingrid Verbauwhede; Shreyas Sen (IEEE J. Solid State Circuits, 2023)

PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing. - Dong-Hyun Seo; Archisman Ghosh; Debayan Das; Mayukh Nath; Santosh Ghosh; Shreyas Sen (IEEE Open J. Circuits Syst., 2023)

BipBip: A Low-Latency Tweakable Block Cipher with Small Dimensions. - Yanis Belkheyar; Joan Daemen; Christoph Dobraunig; Santosh Ghosh; Shahram Rasoolzadeh (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023)

A novel methodology for the planning of charging infrastructure in the scenario of high EV penetration. - Mandhir Kumar Verma; Vivekananda Mukherjee; Vinod Kumar Yadav; Santosh Ghosh (Soft Comput., 2023)

A Unified Cryptoprocessor for Lattice-Based Signature and Key-Exchange. - Aikata; Ahmet Can Mert; David Jacquemin; Amitabh Das; Donald Matthews; Santosh Ghosh; Sujoy Sinha Roy (IEEE Trans. Computers, 2023)

Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing. - Dong-Hyun Seo; Mayukh Nath; Debayan Das; Santosh Ghosh; Shreyas Sen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Koala: A Low-Latency Pseudorandom Function. - Parisa Amiri-Eliasi; Yanis Belkheyar; Joan Daemen; Santosh Ghosh; Daniël Kuijsters; Alireza Mehrdad; Silvia Mella; Shahram Rasoolzadeh; Gilles Van Assche (IACR Cryptol. ePrint Arch., 2024)

Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Towards Power and EM SCA Resilience. - Archisman Ghosh; Md. Abdur Rahman; Debayan Das; Santosh Ghosh; Shreyas Sen (IACR Cryptol. ePrint Arch., 2024)

R-STELLAR: A Resilient Synthesizable Signature Attenuation SCA Protection on AES-256 with built-in Attack-on-Countermeasure Detection. - Archisman Ghosh; Dong-Hyun Seo; Debayan Das; Santosh Ghosh; Shreyas Sen (IACR Cryptol. ePrint Arch., 2024)

Switch Capacitor-Based Time-Varying Transfer Function for FCN and CNN MLSCA-Resistant AES256 in 65-nm CMOS. - Archisman Ghosh; Debayan Das; Santosh Ghosh; Shreyas Sen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring. - Pooya Aghanoury; Santosh Ghosh; Nader Sehatbakhsh (IEEE Comput. Archit. Lett., 2025)