Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. - Santosh Kumar Vishvakarma; V. Komal Kumar; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2011)

Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin. - Chandrabhan Kushwah; Santosh Kumar Vishvakarma (VDAT, 2012)

Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions. - Dheeraj Sharma; Santosh Kumar Vishvakarma (Microelectron. J., 2012)

Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM. - Bhupendra Singh Reniwal; Santosh Kumar Vishvakarma (VDAT, 2013)

A sub-threshold eight transistor (8T) SRAM cell design for stability improvement. - C. B. Kushwah; Santosh Kumar Vishvakarma (ICICDT, 2014)

Single-ended sub-threshold finfet 7T SRAM cell without boosted supply. - C. B. Kushwah; Santosh Kumar Vishvakarma; Devesh Dwivedi (ICICDT, 2014)

Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. - Bhupendra Singh Reniwal; Vikas Vijayvargiya; Pooran Singh; Santosh Kumar Vishvakarma; Devesh Dwivedi (ACM Great Lakes Symposium on VLSI, 2015)

Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. - Neha Jagwani; Vikas Vijayvargiya; Santosh Kumar Vishvakarma (iNIS, 2015)

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. - Santosh Kumar Vishvakarma; Bhupendra Singh Reniwal; V. Sharma; C. B. Khuswah; Devesh Dwivedi (iNIS, 2015)

An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. - Praneet Bhatia; Bhupendra Singh Reniwal; Santosh Kumar Vishvakarma (VDAT, 2015)

Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. - Dheeraj Sharma; Santosh Kumar Vishvakarma (Microelectron. J., 2015)

Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. - Shraddha Thakre; Ankur Beohar; Vikas Vijayvargiya; Nandakishor Yadav; Santosh Kumar Vishvakarma (iNIS, 2016)

Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. - Nandakishor Yadav; Ankur Beohar; Santosh Kumar Vishvakarma (iNIS, 2016)

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications. - C. B. Kushwah; Santosh Kumar Vishvakarma; Devesh Dwivedi (Circuits Syst. Signal Process., 2016)

Ultra-Fast Current Mode Sense Amplifier for Small (I_{ mathrm{CELL}} ) SRAM in FinFET with Improved Offset Tolerance. - Bhupendra Singh Reniwal; Vikas Vijayvargiya; Santosh Kumar Vishvakarma; Devesh Dwivedi (Circuits Syst. Signal Process., 2016)

A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. - C. B. Kushwah; Santosh Kumar Vishvakarma; Devesh Dwivedi (Microelectron. J., 2016)

A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. - C. B. Kushwah; Santosh Kumar Vishvakarma (IEEE Trans. Very Large Scale Integr. Syst., 2016)

LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. - Ambika Prasad Shah; Nandakishor Yadav; Santosh Kumar Vishvakarma (VDAT, 2017)

A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. - Bhupendra Singh Reniwal; Pooran Singh; Vikas Vijayvargiya; Santosh Kumar Vishvakarma (VLSID, 2017)

Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. - Pooran Singh; Bhupendra Singh Reniwal; Vikas Vijayvargiya; V. Sharma; Santosh Kumar Vishvakarma (J. Low Power Electron., 2017)

Design and investigation of variability aware sense amplifier for low power, high speed SRAM. - Bhupendra Singh Reniwal; Praneet Bhatia; Santosh Kumar Vishvakarma (Microelectron. J., 2017)

Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. - Aditya Japa; T. Nagateja; Santosh Kumar Vishvakarma; Yellappa Palagani; Jun Rim Choi; Ramesh Vaddi (ISCAS, 2018)

A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. - Jai Gopal Pandey; Tarun Goel; Mausam Nayak; Chhavi Mitharwal; Sajid Khan 001; Santosh Kumar Vishvakarma; Abhijit Karmakar; Raj Singh (VDAT, 2018)

A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. - Vishal Sharma 004; Pranshu Bisht; Abhishek Dalal; Shailesh Singh Chouhan; H. S. Jattana; Santosh Kumar Vishvakarma (VDAT, 2018)

Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System. - Pooran Singh; Santosh Kumar Vishvakarma (IEEE Access, 2018)

Robust task-space motion control of a mobile manipulator using a nonlinear control with an uncertainty estimator. - S. Mishra; Pandurang S. Londhe; Mohan Santhakumar; Santosh Kumar Vishvakarma; B. M. Patre (Comput. Electr. Eng., 2018)

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes. - Vishal Sharma 004; Santosh Kumar Vishvakarma; Shailesh Singh Chouhan; Kari Halonen (Int. J. Circuit Theory Appl., 2018)

Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. - Pooran Singh; Bhupendra Singh Reniwal; Vikas Vijayvargiya; V. Sharma; Santosh Kumar Vishvakarma (Integr., 2018)

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. - Ambika Prasad Shah; Nandakishor Yadav; Ankur Beohar; Santosh Kumar Vishvakarma (Microelectron. Reliab., 2018)

Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. - Ankur Beohar; Gopal Raut; Gunjan Rajput; Abhinav Vishwakarma; Ambika Prasad Shah; Bhupendra Singh Reniwal; Santosh Kumar Vishvakarma (VDAT, 2019)

Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. - Neha Gupta; Tanisha Gupta; Sajid Khan 001; Abhinav Vishwakarma; Santosh Kumar Vishvakarma (VDAT, 2019)

A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell. - Neha Gupta; Jitesh Prasad; Rana Sagar Kumar; Gunjan Rajput; Santosh Kumar Vishvakarma (VDAT, 2019)

An Ultra Low Power AES Architecture for IoT. - Sajid Khan 001; Neha Gupta; Gopal Raut; Gunjan Rajput; Jai Gopal Pandey; Santosh Kumar Vishvakarma (VDAT, 2019)

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. - Sajid Khan 001; Neha Gupta; Abhinav Vishwakarma; Shailesh Singh Chouhan; Jai Gopal Pandey; Santosh Kumar Vishvakarma (VDAT, 2019)

Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. - Gopal Raut; Vishal Bhartiy; Gunjan Rajput; Sajid Khan 001; Ankur Beohar; Santosh Kumar Vishvakarma (VDAT, 2019)

An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. - Bhupendra Singh Reniwal; Vikas Vijayvargiya; Pooran Singh; Nand Kishor Yadav; Santosh Kumar Vishvakarma; Devesh Dwivedi (Circuits Syst. Signal Process., 2019)

SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit. - Ambika Prasad Shah; Nandakishor Yadav; Ankur Beohar; Santosh Kumar Vishvakarma (IET Comput. Digit. Tech., 2019)

An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. - Sajid Khan 001; Ambika Prasad Shah; Neha Gupta; Shailesh Singh Chouhan; Jai Gopal Pandey; Santosh Kumar Vishvakarma (Microelectron. J., 2019)

An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network. - Prachi Sanvale; Neha Gupta; Vaibhav Neema; Ambika Prasad Shah; Santosh Kumar Vishvakarma (Microelectron. J., 2019)

IoT-Based Ambient Intelligence Microcontroller for Remote Temperature Monitoring. - Balwinder Raj; Jeetendra Singh; Santosh Kumar Vishvakarma; Shailesh Singh Chouhan (Guide to Ambient Intelligence in the IoT Environment, 2019)

A CORDIC Based Configurable Activation Function for ANN Applications. - Gopal Raut; Shubham Rai; Santosh Kumar Vishvakarma; Akash Kumar 001 (ISVLSI, 2020)

A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. - Gopal Raut; Ambika Prasad Shah; Vishal Sharma 004; Gunjan Rajput; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2020)

Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications. - Ambika Prasad Shah; Santosh Kumar Vishvakarma; Michael Hübner 001 (J. Electron. Test., 2020)

An improved current mode logic latch for high-speed applications. - Mahesh Kumawat; Abhishek Kumar Upadhyay; Sanjay Sharma; Ravi Kumar 006; Gaurav Singh; Santosh Kumar Vishvakarma (Int. J. Commun. Syst., 2020)

A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. - Mahesh Kumawat; Mohit Singh Choudhary; Ravi Kumar 006; Gaurav Singh; Santosh Kumar Vishvakarma (J. Circuits Syst. Comput., 2020)

Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. - Jyoti Bhatia; Aveen Dayal; Ajit Jha; Santosh Kumar Vishvakarma; Soumya J.; M. B. Srinivas; Phaneendra K. Yalavarthy; Abhinav Kumar 001; V. Lalitha 001; Sagar Koorapati; Linga Reddy Cenkeramaddi (COMSNETS, 2021)

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. - Neha Gupta; Nikhil Agrawal; Narendra Singh Dhakad; Ambika Prasad Shah; Santosh Kumar Vishvakarma; Patrick Girard 001 (ACM Great Lakes Symposium on VLSI, 2021)

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies. - Shubham Rai; Pallab Nath; Ansh Rupani; Santosh Kumar Vishvakarma; Akash Kumar 001 (IEEE Access, 2021)

VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators. - Gunjan Rajput; Gopal Raut; Mahesh Chandra; Santosh Kumar Vishvakarma (Microprocess. Microsystems, 2021)

RECON: Resource-Efficient CORDIC-Based Neuron Architecture. - Gopal Raut; Shubham Rai; Santosh Kumar Vishvakarma; Akash Kumar 001 (IEEE Open J. Circuits Syst., 2021)

Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture". - Gopal Raut; Shubham Rai; Santosh Kumar Vishvakarma; Akash Kumar 001 (IEEE Open J. Circuits Syst., 2021)

Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array. - Varun Bhatnagar; Gopal Raut; Santosh Kumar Vishvakarma (ACM Great Lakes Symposium on VLSI, 2022)

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. - Nikhil Rangarajan; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Shubham Rai; Gopal Raut; Heba Abunahla; Baker Mohammad; Santosh Kumar Vishvakarma; Akash Kumar 001; Johann Knechtel; Ozgur Sinanoglu (ISVLSI, 2022)

An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. - S. Kavitha; Santosh Kumar Vishvakarma; Bhupendra Singh Reniwal (VDAT, 2022)

BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator. - Harsh Chhajed; Gopal Raut; Narendra Singh Dhakad; Sudheer Vishwakarma; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2022)

SCAN: Streamlined Composite Activation Function Unit for Deep Neural Accelerators. - Gunjan Rajput; Kunika Naresh Biyani; V. Logashree; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2022)

Data multiplexed and hardware reused architecture for deep neural network accelerator. - Gopal Raut; Anton Biasizzo; Narendra Singh Dhakad; Neha Gupta; Gregor Papa; Santosh Kumar Vishvakarma (Neurocomputing, 2022)

Early breast cancer diagnosis using cogent activation function-based deep learning implementation on screened mammograms. - Gunjan Rajput; Shashank Agrawal; Kunika Naresh Biyani; Santosh Kumar Vishvakarma (Int. J. Imaging Syst. Technol., 2022)

An accurate and noninvasive skin cancer screening based on imaging technique. - Gunjan Rajput; Shashank Agrawal; Gopal Raut; Santosh Kumar Vishvakarma (Int. J. Imaging Syst. Technol., 2022)

A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators. - Sudheer Vishwakarma; Gopal Raut; Narendra Singh Dhakad; Santosh Kumar Vishvakarma; Dhruva Ghai (IFIPIoT (1), 2023)

Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. - Mohd Sakib Ansari S; Kavitha S; Bhupendra Singh Reniwal; Santosh Kumar Vishvakarma (VLSID, 2023)

An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning. - Sumiran Mehra; Gopal Raut; Ribhu Das Purkayastha; Santosh Kumar Vishvakarma; Anton Biasizzo (IEEE Access, 2023)

Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array. - Kavitha Soundrapandiyan; Santosh Kumar Vishvakarma; Bhupendra Singh Reniwal (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic. - Ravi Kumar; Pooja Bohara; Krishna Thakur; Santosh Kumar Vishvakarma (J. Circuits Syst. Comput., 2023)

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency. - Ravi Kumar 006; Rajasekhar Nagulapalli; Santosh Kumar Vishvakarma (J. Circuits Syst. Comput., 2023)

An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks. - Gopal Raut; Saurabh Karkun; Santosh Kumar Vishvakarma (ACM Trans. Reconfigurable Technol. Syst., 2023)

Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators. - Gunjan Rajput; V. Logashree; Kunika Naresh Biyani; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2023)

Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. - Gopal Raut; Jogesh Mukala; Vishal Sharma 004; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2023)

Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs. - Vasundhara Trivedi; Khushbu Lalwani; Gopal Raut; Avikshit Khomane; Neha Ashar; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2023)

HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine. - Omkar Kokane; Prabhat Sati; Mukul Lokhande; Santosh Kumar Vishvakarma (VDAT, 2024)

QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit. - Neha Ashar; Gopal Raut; Vasundhara Trivedi; Santosh Kumar Vishvakarma; Akash Kumar 001 (IEEE Access, 2024)

Configurable Multi-Port Memory Architecture for High-Speed Data Communication. - Narendra Singh Dhakad; Santosh Kumar Vishvakarma (CoRR, 2024)

SHA-CNN: Scalable Hierarchical Aware Convolutional Neural Network for Edge AI. - Narendra Singh Dhakad; Yuvnish Malhotra; Santosh Kumar Vishvakarma; Kaushik Roy (CoRR, 2024)

HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator. - Sonu Kumar; Komal Gupta; Gopal Raut; Mukul Lokhande; Santosh Kumar Vishvakarma (CoRR, 2024)

Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads. - Mukul Lokhande; Gopal Raut; Santosh Kumar Vishvakarma (CoRR, 2024)

In-Memory Computing with 6T SRAM for Multi-operator Logic Design. - Narendra Singh Dhakad; Eshika Chittora; Gopal Raut; Vishal Sharma 004; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2024)

A Precision-Aware Neuron Engine for DNN Accelerators. - Sudheer Vishwakarma; Gopal Raut; Sonu Jaiswal; Santosh Kumar Vishvakarma; Dhruva Ghai (SN Comput. Sci., 2024)

LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine. - Omkar Kokane; Mukul Lokhande; Gopal Raut; Adam Teman; Santosh Kumar Vishvakarma (ISCAS, 2025)

Area-Optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing. - Akash Sankhe; Mukul Lokhande; Radheshyam Sharma; Santosh Kumar Vishvakarma (ISQED, 2025)

Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. - Omkar Kokane; Gopal Raut; Salim Ullah; Mukul Lokhande; Adam Teman; Akash Kumar 001; Santosh Kumar Vishvakarma (ISVLSI, 2025)

CORDIC Is All You Need. - Omkar Kokane; Adam Teman; Anushka Jha; Guru Prasath SL; Gopal Raut; Mukul Lokhande; S. V. Jaya Chand; Tanushree Dewangan; Santosh Kumar Vishvakarma (CoRR, 2025)

QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine. - Anushka Jha; Tanushree Dewangan; Mukul Lokhande; Santosh Kumar Vishvakarma (CoRR, 2025)

POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration. - Mukul Lokhande; Santosh Kumar Vishvakarma (CoRR, 2025)

Configurable Multiport Memory Architecture for High-Speed Data Communication. - Narendra Singh Dhakad; Santosh Kumar Vishvakarma (IEEE Embed. Syst. Lett., 2025)

Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads. - Mukul Lokhande; Gopal Raut; Santosh Kumar Vishvakarma (IEEE Trans. Very Large Scale Integr. Syst., 2025)

XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads. - Tejas Chaudhari; Akarsh J.; Tanushree Dewangan; Mukul Lokhande; Santosh Kumar Vishvakarma (CoRR, 2025)