Deterministic Algorithm to generate SEC-DED-DAEC H-Matrix for SRAMs in FPGAs for reliable space applications. - Kumar Rahul; Santosh Yachareni (ICCCS, 2020)

Area and power efficient ECC for multiple adjacent bit errors in SRAMs. - Kumar Rahul; Santosh Yachareni (ICCE, 2020)

Mitigation of the impact of across chip systematic process variation using a novel system level design. - Nabanita Ghoshal; Sree Rama K. C. Saraswatula; Santosh Yachareni; Shidong Zhou; Anil Kumar Kandala; Narendra Kumar Pulipati (DFT, 2021)

Robust Adaptive Read Scheme for 7nm Configuration SRAMs. - Sree Rama K. C. Saraswatula; Santosh Yachareni; Shidong Zhou; Narendra Kumar Pulipati; Joy Chen; Teja Masina (IOLTS, 2021)

Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA. - Mahendrakumar Gunasekaran; Kumar Rahul; Santosh Yachareni (ISNCC, 2021)

High speed low power SEU tolerant Pseudo dual port memory in 7nm. - Suresh Babu Kotha; Kumar Rahul; Mohammad Anees; Santosh Yachareni; Subodh Kumar (ISNCC, 2021)

A bidirectional frequency detector independent of input transition density for a wide-tuning range applications. - Abhinav Vajrala; Rajesh Mahadev; Santosh Yachareni; Zia Abbas (ISCAS, 2025)