Energy efficiency limits of logic and memory. - Sapan Agarwal; Jeanine E. Cook; Erik DeBenedictis; Michael P. Frank; Gert Cauwenberghs; Sriseshan Srikanth; Bobin Deng; Eric R. Hein; Paul G. Rabbat; Thomas M. Conte (ICRC, 2016)

Resistive memory device requirements for a neural algorithm accelerator. - Sapan Agarwal; Steven J. Plimpton; David R. Hughart; Alexander H. Hsia; Isaac Richter; Jonathan A. Cox; Conrad D. James; Matthew J. Marinella (IJCNN, 2016)

Neuromemristive Systems: Boosting Efficiency through Brain-Inspired Computing. - Cory E. Merkel; Raqibul Hasan; Nicholas Soures; Dhireesha Kudithipudi; Tarek M. Taha; Sapan Agarwal; Matthew J. Marinella (Computer, 2016)

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator. - Robin B. Jacobs-Gedrim; Sapan Agarwal; Kathrine E. Knisely; Jim E. Stevens; Michael S. van Heukelom; David R. Hughart; John Niroula; Conrad D. James; Matthew J. Marinella (ICRC, 2017)

Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks. - Abdullah M. Zyarah; Nicholas Soures; Lydia Hays; Robin Jacobs-Gedrim; Sapan Agarwal; Matthew J. Marinella; Dhireesha Kudithipudi (ISCAS, 2017)

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator. - Matthew J. Marinella; Sapan Agarwal; Alexander H. Hsia; Isaac Richter; Robin Jacobs-Gedrim; John Niroula; Steven J. Plimpton; Engin Ipek; Conrad D. James (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Wafer-Scale TaOx Device Variability and Implications for Neuromorphic Computing Applications. - Christopher H. Bennett; Diana Garland; Robin B. Jacobs-Gedrim; Sapan Agarwal; Matthew J. Marinella (IRPS, 2019)

Sparse Data Acquisition on Emerging Memory Architectures. - Tu-Thach Quach; Sapan Agarwal; Conrad D. James; Matthew J. Marinella; James B. Aimone (IEEE Access, 2019)

Using Floating Gate Memory to Train Ideal Accuracy Neural Networks. - Sapan Agarwal; Diana Garland; John Niroula; Robin B. Jacobs-Gedrim; Alexander H. Hsia; Michael S. van Heukelom; Elliot J. Fuller; Bruce Draper; Matthew J. Marinella (CoRR, 2019)

Redox transistors for neuromorphic computing. - Elliot J. Fuller; Yiyang Li; Christopher H. Bennett; Scott T. Keene; Armantas Melianas; Sapan Agarwal; Matthew J. Marinella; Alberto Salleo; A. Alec Talin (IBM J. Res. Dev., 2019)

Device-aware inference operations in SONOS nonvolatile memory arrays. - Christopher H. Bennett; T. Patrick Xiao; Ryan Dellana; Ben Feinberg; Sapan Agarwal; Matthew J. Marinella; Vineet Agrawal; Venkatraman Prabhakar; Krishnaswamy Ramkumar; Long Hinh; Swatilekha Saha; Vijay Raghavan; et al. (IRPS, 2020)

Evaluating complexity and resilience trade-offs in emerging memory inference machines. - Christopher H. Bennett; Ryan Dellana; T. Patrick Xiao; Ben Feinberg; Sapan Agarwal; Suma Cardwell; Matthew J. Marinella; William Severa; Brad Aimone (NICE, 2020)

Tunnel-FET Switching Is Governed by Non-Lorentzian Spectral Line Shape. - Sri Krishna Vadlamani; Sapan Agarwal; David T. Limmer; Steven G. Louie; Felix R. Fischer; Eli Yablonovitch (Proc. IEEE, 2020)

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM. - Aayush Ankit; Izzat El Hajj; Sai Rahul Chalamalasetti; Sapan Agarwal; Matthew J. Marinella; Martin Foltin; John Paul Strachan; Dejan S. Milojicic; Wen-Mei Hwu; Kaushik Roy 001 (IEEE Trans. Computers, 2020)

An Analog Preconditioner for Solving Linear Systems. - Ben Feinberg; Ryan Wong 001; T. Patrick Xiao; Christopher H. Bennett; Jacob N. Rohan; Erik G. Boman; Matthew J. Marinella; Sapan Agarwal; Engin Ipek (HPCA, 2021)

On the Accuracy of Analog Neural Network Inference Accelerators. - T. Patrick Xiao; Ben Feinberg; Christopher H. Bennett; Venkatraman Prabhakar; Prashant Saxena; Vineet Agrawal; Sapan Agarwal; Matthew J. Marinella (CoRR, 2021)

Analog Neural Network Inference Accuracy in One-Selector One-Resistor Memory Arrays. - Joshua E. Kim; T. Patrick Xiao; Christopher H. Bennett; Donald Wilson; Matthew Spear; Maximilian Siath; Ben Feinberg; Sapan Agarwal; Matthew J. Marinella (ICRC, 2022)

ATHENA: Enabling Codesign for Next-Generation AI/ML Architectures. - Mark Plagge; Ben Feinberg; John McFarland; Fred Rothganger; Sapan Agarwal; Amro Awad; Clayton Hughes; Suma George Cardwell (ICRC, 2022)

Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology. - Lawrence T. Clark; Alen Duvnjak; Clifford Young-Sciortino; Matthew Cannon; John S. Brunhaver; Sapan Agarwal; Jereme Neuendank; Donald Wilson; Hugh J. Barnaby; Matthew J. Marinella (ISCAS, 2022)

Eris: Fault Injection and Tracking Framework for Reliability Analysis of Open-Source Hardware. - Shubham Nema; Justin Kirschner; Debpratim Adak; Sapan Agarwal; Ben Feinberg; Arun F. Rodrigues; Matthew J. Marinella; Amro Awad (ISPASS, 2022)

An out-of-distribution discriminator based on Bayesian neural network epistemic uncertainty. - Ethan Ancell; Christopher H. Bennett; Bert J. Debusschere; Sapan Agarwal; Park Hays; T. Patrick Xiao (CoRR, 2022)

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory. - T. Patrick Xiao; Ben Feinberg; Christopher H. Bennett; Vineet Agrawal; Prashant Saxena; Venkatraman Prabhakar; Krishnaswamy Ramkumar; Harsha Medu; Vijay Raghavan; Ramesh Chettuvetty; Sapan Agarwal; Matthew J. Marinella (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Statistical Characterization of ReRAM Arrays for Analog In-Memory Computing. - Jesse Short; Matthew Spear; Donald Wilson; William Wahby; T. Patrick Xiao; Robin Jacobs-Gedrim; Christopher H. Bennett; Nad Gilbert; Sapan Agarwal; Matthew J. Marinella (ICRC, 2023)

TID Response of an Analog In-Memory Neural Network Accelerator. - B. Tolleson; Christopher H. Bennett; T. Patrick Xiao; Donald Wilson; Jesse Short; Joshua E. Kim; David R. Hughart; Nad Gilbert; Sapan Agarwal; Hugh J. Barnaby; Matthew J. Marinella (IRPS, 2023)

Enabling High-Speed, High-Resolution Space-based Focal Plane Arrays with Analog In-Memory Computing. - T. Patrick Xiao; W. S. Wahby; Christopher H. Bennett; Park Hays; V. Agrawal; Matthew J. Marinella; Sapan Agarwal (VLSI Technology and Circuits, 2023)

Understanding and Manipulating Electronic Noise in Electrochemical Random Access Memory for Neuromorphic Computing. - Sangheon Oh; T. Patrick Xiao; Christopher H. Bennett; Patrick S. Finnegan; Sean R. Bishop; Adam S. Christensen; Adam L. Gross; Sangyong Lee; Andrew Jalbert; Leah Simakas; Joshua D. Sugar; Yiyang Li; et al. (DRC, 2024)

SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator. - Pragnya Sudershan Nalla; Zhenyu Wang; Sapan Agarwal; T. Patrick Xiao; Christopher H. Bennett; Matthew J. Marinella; Jae-sun Seo; Yu Cao 001 (ISVLSI, 2024)

Biological Dynamics Enabling Training of Binary Recurrent Networks. - G. William Chapman; Corinne Teeter; Sapan Agarwal; T. Patrick Xiao; Park Hays; Srideep Musuvathy (NICE, 2024)

TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives. - Ryan Wong 001; Nikita Kim; Kevin Higgs; Sapan Agarwal; Engin Ipek; Saugata Ghose; Ben Feinberg (CoRR, 2024)

Analog fast Fourier transforms for scalable and efficient signal processing. - T. Patrick Xiao; Ben Feinberg; David K. Richardson; Matthew Cannon; Harsha Medu; Vineet Agrawal; Matthew J. Marinella; Sapan Agarwal; Christopher H. Bennett (CoRR, 2024)

ANVIL: An In-Storage Accelerator for Name-Value Data Stores. - Ryan Wong 001; Nikita Kim; Aniket Das; Kevin Higgs; Engin Ipek; Sapan Agarwal; Saugata Ghose; Ben Feinberg (ISCA, 2025)

Analog Bayesian neural networks are insensitive to the shape of the weight distribution. - Ravi G. Patel; T. Patrick Xiao; Sapan Agarwal; Christopher H. Bennett (CoRR, 2025)

Self-heating electrochemical memory for high-precision analog computing. - Adam L. Gross; Sangheon Oh; François Léonard; Wyatt Hodges; T. Patrick Xiao; Joshua D. Sugar; Jacklyn Zhu; Sritharini Radhakrishnan; Sangyong Lee; Jolie Wang; Adam S. Christensen; Sam Lilak; et al. (CoRR, 2025)