Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. - Alexander Fell; Mythri Alle; Keshavan Varadarajan; Prasenjit Biswas; Saptarsi Das; Jugantor Chetia; S. K. Nandy 001; Ranjani Narayan (CASES, 2009)

REDEFINE: Runtime reconfigurable polymorphic ASIC. - Mythri Alle; Keshavan Varadarajan; Alexander Fell; C. Ramesh Reddy; Joseph Nimmy; Saptarsi Das; Prasenjit Biswas; Jugantor Chetia; Adarsha Rao; S. K. Nandy 001; Ranjani Narayan (ACM Trans. Embed. Comput. Syst., 2009)

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. - Saptarsi Das; Ranjani Narayan; Soumitra Kumar Nandy (ICETE (Selected Papers), 2011)

A Method for Flexible Reduction over Binary Fields using a Field Multiplier. - Saptarsi Das; Keshavan Varadarajan; Ganesh Garga; Rajdeep Mondal; Ranjani Narayan; S. K. Nandy 001 (SECRYPT, 2011)

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. - Ratna Krishnamoorthy; Saptarsi Das; Keshavan Varadarajan; Mythri Alle; Masahiro Fujita; Soumitra Kumar Nandy; Ranjani Narayan (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. - Kavitha T. Madhu; Saptarsi Das; Madhava Krishna C; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2014)

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. - Saptarsi Das; Kavitha T. Madhu; Madhav Krishna; Nalesh Sivanandan; Farhad Merchant; Santhi Natarajan; Ipsita Biswas; Adithya Pulli; S. K. Nandy 001; Ranjani Narayan (J. Syst. Archit., 2014)

Compiling HPC Kernels for the REDEFINE CGRA. - Kavitha T. Madhu; Saptarsi Das; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (HPCC/CSS/ICESS, 2015)

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (iNIS, 2015)

Flexible resource allocation and management for application graphs on ReNÉ MPSoC. - Kavitha T. Madhu; Anuj Rao; Saptarsi Das; Krishna C. Madhava; S. K. Nandy 001; Ranjani Narayan (PARMA-DITAM@HiPEAC, 2016)

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. - Saptarsi Das; Nalesh Sivanandan; Kavitha T. Madhu; Soumitra Kumar Nandy; Ranjani Narayan (VLSID, 2016)

Energy aware synthesis of application kernels through composition of data-paths on a CGRA. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (Integr., 2017)

A Systolic Dataflow Based Accelerator for CNNs. - Saptarsi Das; Arnab Roy 010; Kiran Kolar Chandrasekharan; Ankur Deshwal; Sehwan Lee (ISCAS, 2020)

Transport Triggered near Memory Accelerator for Deep Learning. - Kavitha T. Madhu; Saptarsi Das; Abhishek Tyagi; Ankur Deshwal; Joonho Song; Seungwon Lee (ISCAS, 2021)