Area-optimal sensing circuit designs in deep submicrometer STT-RAM. - Sara Choi; Taehui Na; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISCAS, 2016)

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. - Sara Choi; Taehui Na; Jisu Kim; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region. - Byungkyu Song; Sara Choi; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. - Sara Choi; Hong Keun Ahn; Byungkyu Song; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. - Taehui Na; Byungkyu Song; Sara Choi; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC. - Giseok Kim; Ki-Ryong Kim; Sara Choi; Hyo Jung Jang; Seong-Ook Jung (IEEE Access, 2020)

Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. - Sara Choi; Hong Keun Ahn; Byungkyu Song; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface. - Moosung Kim; Sung-Won Yun; Jungjune Park; Hyun Kook Park; Jungyu Lee 002; Yeong Seon Kim; Dae-Hoon Na; Sara Choi; Youngsun Song; Jonghoon Lee; Hyun-Jun Yoon; Kangbin Lee; et al. (ISSCC, 2022)