Modeling the Impact of Checkpoints on Next-Generation Systems. - Ron A. Oldfield; Sarala Arunagiri; Patricia J. Teller; Seetharami R. Seelam; Maria Ruiz Varela; Rolf Riesen; Philip C. Roth (MSST, 2007)

Modeling and Analysis of Checkpoint I/O Operations. - Sarala Arunagiri; John T. Daly; Patricia J. Teller (ASMTA, 2009)

FAIRIO: An Algorithm for Differentiated I/O Performance. - Sarala Arunagiri; Yipkei Kwok; Patricia J. Teller; Ricardo Portillo; Seetharami R. Seelam (SBAC-PAD, 2011)

Evaluation of Core Performance when the Node is Power Capped Using Intel® Data Center Manager. - Joshua McCartney; Patricia J. Teller; Sarala Arunagiri (ICPP Workshops, 2012)

Power and execution performance tradeoffs of GPGPU computing: a case study employing stereo matching. - Sarala Arunagiri; Jaime Jaloma; Ricardo Portillo; Arturo Argueta (Image Processing: Machine Vision Applications, 2013)

Parallel GPGPU stereo matching with an energy-efficient cost function based on normalized cross correlation. - Sarala Arunagiri; Jaime Jaloma (Image Processing: Algorithms and Systems, 2013)

FAIRIO: A Throughput-oriented Algorithm for Differentiated I/O Performance. - Sarala Arunagiri; Yipkei Kwok; Patricia J. Teller; Ricardo Portillo; Seetharami R. Seelam (Int. J. Parallel Program., 2014)

2TL: A Scheduling Algorithm for Meeting the Latency Requirements of Bursty I/O Streams at User-Specified Percentiles. - Yipkei Kwok; Patricia J. Teller; Sarala Arunagiri (ICCAC, 2017)