Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. - Paul Chang; Brion L. Keller; Sarala Paliwal (ICCD, 1999)

Effective parallel processing techniques for the generation of test data for a logic built-in self test system. - Paul Chang; Brion L. Keller; Sarala Paliwal (Asian Test Symposium, 2000)

Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. - Robert Butler; Brion L. Keller; Sarala Paliwal; Richard Schoonover; Joseph Swenton (ITC, 2000)

SEAS: a system for early analysis of SoCs. - Reinaldo A. Bergamaschi; Youngsoo Shin; Nagu R. Dhanwada; Subhrajit Bhattacharya; William E. Dougherty; Indira Nair; John A. Darringer; Sarala Paliwal (CODES+ISSS, 2003)