VAET-STT: A variation aware estimator tool for STT-MRAM based memories. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mohammad Saber Golanbari; Fabian Oboril; Mehdi Baradaran Tahoori (DATE, 2017)

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Sophiane Senni; Jad Mohdad; Frédérick Mailly; Lionel Torres; Pascal Benoit; Pascal Nouet; Rui Ma; Martin Kreißig; Frank Ellinger; et al. (ISVLSI, 2017)

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. - Nour Sayed; Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (ASP-DAC, 2018)

Parametric failure modeling and yield analysis for STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (DATE, 2018)

Using multifunctional standardized stack as universal spintronic technology for IoT. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Sophiane Senni; Jad Mohdad; Frédérick Mailly; Lionel Torres; Pascal Benoit; Abdoulaye Gamatié; Pascal Nouet; Frederic Ouattara; Gilles Sassatelli; et al. (DATE, 2018)

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Grigor Tshagharyan; Hayk T. Grigoryan; Gurgen Harutyunyan; Yervant Zorian (ITC, 2018)

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mohammad Saber Golanbari; Fabian Oboril; Fazal Hameed; Mehdi Baradaran Tahoori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Variation-aware Fault Modeling and Test Generation for STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Hayk T. Grigoryan; Grigor Tshagharyan (IOLTS, 2019)

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori; Houman Zahedmanesh; Kristof Croes; Kevin Garello; Gouri Sankar Kar; Francky Catthoor (IRPS, 2019)

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit. - Samir Ben Dodo; Rajendra Bishnoi; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Dynamic Faults based Hardware Trojan Design in STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Arunkumar Vijayan; Mehdi Baradaran Tahoori (DATE, 2020)

A Universal Spintronic Technology based on Multifunctional Standardized Stack. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Lionel Torres; Sophiane Senni; Guillaume Patrigeon; Pascal Benoit; Gregory di Pendina; Guillaume Prenat (DATE, 2020)

Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory. - Sarath Mohanachandran Nair; Christopher Münch; Mehdi Baradaran Tahoori (ETS, 2020)

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi B. Tahoori; Houman Zahedmanesh; Kristof Croes; Kevin Garello; Gouri Sankar Kar; Francky Catthoor (IRPS, 2020)

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. - Rajendra Bishnoi; Lizhou Wu; Moritz Fieback; Christopher Münch; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori; Ying Wang 001; Huawei Li 001; Said Hamdioui (VTS, 2020)

Mitigating Read Failures in STT-MRAM. - Sarath Mohanachandran Nair; Rajendra Bishnoi; Mehdi Baradaran Tahoori (VTS, 2020)

Variation Analysis, Fault Modeling and Yield Improvement of Emerging Spintronic Memories - Sarath Mohanachandran Nair (2020)