A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. - Sari Onaissi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Clock skew optimization via wiresizing for timing sign-off covering all process corners. - Sari Onaissi; Khaled R. Heloue; Farid N. Najm (DAC, 2009)

PSTA-based branch and bound approach to the silicon speedpath isolation problem. - Sari Onaissi; Khaled R. Heloue; Farid N. Najm (ICCAD, 2009)

A fast approach for static timing analysis covering all PVT corners. - Sari Onaissi; Feroze Taraporevala; Jinfeng Liu; Farid N. Najm (DAC, 2011)

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. - Khaled R. Heloue; Sari Onaissi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)