Implementation of a programmable neuron in 0.35μm CMOS process for multi-layer ANN applications. - Sarkis Azizian; Karim Fathi; Behbood Mashoufi; Fardin Derogarian (EUROCON, 2011)

CMOS implementation of a fast 4-2 compressor for parallel accumulations. - Amir Fathi; Sarkis Azizian; Khayrollah Hadidi; Abdollah Khoei; Amin Chegeni (ISCAS, 2012)

Low latency, glitch-free booth encoder-decoder for high speed multipliers. - Amir Fathi; Sarkis Azizian; Rahim Fathi; Habib Ghasemizadeh Tamar (IEICE Electron. Express, 2012)

Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations. - Amir Fathi; Sarkis Azizian; Khayrollah Hadidi; Abdollah Khoei (IEICE Trans. Electron., 2012)

A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations. - Amir Fathi; Sarkis Azizian; Khayrollah Hadidi; Abdollah Khoei (IEICE Trans. Electron., 2012)

Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs. - Sarkis Azizian; Mehdi Ehsanian (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations. - Amir Fathi; Behbood Mashoufi; Sarkis Azizian (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Effective extraction method for triple errors in foreground calibration of TI-ADCs. - Sarkis Azizian; Mehdi Ehsanian (Int. J. Circuit Theory Appl., 2022)