BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. - Yung-Te Lai; Massoud Pedram; Sarma B. K. Vrudhula (DAC, 1993)

FGILP: an integer linear program solver based on function graphs. - Yung-Te Lai; Massoud Pedram; Sarma B. K. Vrudhula (ICCAD, 1993)

Analysis of signal probability in logic circuits using stochastic models. - Amitava Majumdar 001; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 1993)

A design of a fast and area efficient multi-input Muller C-element. - T.-Y. Wuu; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Techniques for estimating test length under random test. - Amitava Majumdar 001; Sarma B. K. Vrudhula (J. Electron. Test., 1994)

Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. - King C. Ho; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. - Yung-Te Lai; Massoud Pedram; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Fault Coverage and Test Length Estimation for Random Pattern Testing. - Amitava Majumdar 001; Sarma B. K. Vrudhula (IEEE Trans. Computers, 1995)

Multi-level logic optimization for low power using local logic transformations. - Qi Wang; Sarma B. K. Vrudhula (ICCAD, 1996)

Formal Verification Using Edge-Valued Binary Decision Diagrams. - Yung-Te Lai; Massoud Pedram; Sarma B. K. Vrudhula (IEEE Trans. Computers, 1996)

An Investigation of Power Delay Trade-Offs on PowerPC Circuits. - Qi Wang; Sarma B. K. Vrudhula; Shantanu Ganguly (DAC, 1997)

Macro-instruction generation for dynamic logic caching. - K. McCarley; Sarma B. K. Vrudhula (IEEE International Workshop on Rapid System Prototyping, 1997)

Rapid prototyping of networks of asynchronous multiple functional units. - E. Tsun; Sarma B. K. Vrudhula (IEEE International Workshop on Rapid System Prototyping, 1997)

Data Driven Power Optimization of Sequential Circuits. - Qi Wang; Sarma B. K. Vrudhula (DATE, 1998)

Static power optimization of deep submicron CMOS circuits for dual VT technology. - Qi Wang; Sarma B. K. Vrudhula (ICCAD, 1998)

On short circuit power estimation of CMOS inverters. - Qi Wang; Sarma B. K. Vrudhula (ICCD, 1998)

A Technique for Estimating Signal Activity in Logic Circuits. - Hong-Yu Xie; Sarma B. K. Vrudhula (Integr. Comput. Aided Eng., 1998)

An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. - Qi Wang; Sarma B. K. Vrudhula (ICCD, 1999)

Power reduction and power-delay trade-offs using logic transformations. - Qi Wang; Sarma B. K. Vrudhula; Gary K. H. Yeap; Shantanu Ganguly (ACM Trans. Design Autom. Electr. Syst., 1999)

Adaptive Multiuser Online Reconfigurable Engine. - Daler N. Rakhmatov; Sarma B. K. Vrudhula; Thomas J. Brown; Ajay Nagarandal (IEEE Des. Test Comput., 2000)

An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. - Daler N. Rakhmatov; Sarma B. K. Vrudhula (ICCAD, 2001)

Minimizing routing configuration cost in dynamically reconfigurable FPGAs. - Daler N. Rakhmatov; Sarma B. K. Vrudhula (IPDPS, 2001)

Time-to-failure estimation for batteries in portable electronic systems. - Daler N. Rakhmatov; Sarma B. K. Vrudhula (ISLPED, 2001)

Hardware-software bipartitioning for dynamically reconfigurable systems. - Daler N. Rakhmatov; Sarma B. K. Vrudhula (CODES, 2002)

Battery-conscious task sequencing for portable devices including voltage/clock scaling. - Daler N. Rakhmatov; Sarma B. K. Vrudhula; Chaitali Chakrabarti (DAC, 2002)

Estimation of the likelihood of capacitive coupling noise. - Sarma B. K. Vrudhula; David T. Blaauw; Supamas Sirichotiyakul (DAC, 2002)

Estimation of signal arrival times in the presence of delay noise. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; David T. Blaauw (ICCAD, 2002)

Battery lifetime prediction for energy-aware computing. - Daler N. Rakhmatov; Sarma B. K. Vrudhula; Deborah A. Wallach (ISLPED, 2002)

Statistical timing analysis using bounds and selective enumeration. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Sarma B. K. Vrudhula (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. - Qi Wang; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Behavioral synthesis of field programmable analog array circuits. - Haibo Wang 005; Sarma B. K. Vrudhula (ACM Trans. Design Autom. Electr. Syst., 2002)

Computation and Refinement of Statistical Bounds on Circuit Delay. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Sarma B. K. Vrudhula (DAC, 2003)

Statistical Timing Analysis Using Bounds. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Sarma B. K. Vrudhula (DATE, 2003)

AU: Timing Analysis Under Uncertainty. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; David T. Blaauw (ICCAD, 2003)

Analysis of discharge techniques for multiple battery systems. - Ravishankar Rao; Sarma B. K. Vrudhula; Daler N. Rakhmatov (ISLPED, 2003)

Battery Modeling for Energy-Aware System Design. - Ravishankar Rao; Sarma B. K. Vrudhula; Daler N. Rakhmatov (Computer, 2003)

Probabilistic analysis of interconnect coupling noise. - Sarma B. K. Vrudhula; David T. Blaauw; Supamas Sirichotiyakul (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Energy management for battery-powered embedded systems. - Daler N. Rakhmatov; Sarma B. K. Vrudhula (ACM Trans. Embed. Comput. Syst., 2003)

A model for battery lifetime analysis for organizing applications on a pocket computer. - Daler N. Rakhmatov; Sarma B. K. Vrudhula; Deborah A. Wallach (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Disk drive energy optimization for audio-video applications. - Ravishankar Rao; Sarma B. K. Vrudhula; Musaravakkam S. Krishnan (CASES, 2004)

Variational delay metrics for interconnect timing analysis. - Kanak Agarwal 001; Dennis Sylvester; David T. Blaauw; Frank Liu 001; Sani R. Nassif; Sarma B. K. Vrudhula (DAC, 2004)

Implicit pseudo boolean enumeration algorithms for input vector control. - Kaviraj Chopra; Sarma B. K. Vrudhula (DAC, 2004)

A methodology to improve timing yield in the presence of process variations. - Sreeja Raj; Sarma B. K. Vrudhula; Janet Meiling Wang (DAC, 2004)

A Framework for Battery-Aware Sensor Management. - Sridhar Dasika; Sarma B. K. Vrudhula; Kaviraj Chopra; R. Srinivasan (DATE, 2004)

Energy optimization for a two-device data flow chain. - Ravishankar Rao; Sarma B. K. Vrudhula (ICCAD, 2004)

Stochastic analysis of interconnect performance in the presence of process variations. - Janet Meiling Wang; Praveen Ghanta; Sarma B. K. Vrudhula (ICCAD, 2004)

Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. - Kaviraj Chopra; Sarma B. K. Vrudhula; Sarvesh Bhardwaj (VLSI Design, 2004)

Energy Profiler for Hardware/Software Co-Design. - Raghukiran Sreeramaneni; Sarma B. K. Vrudhula (VLSI Design, 2004)

Leakage minimization of nano-scale circuits in the presence of systematic and random variations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (DAC, 2005)

Energy optimal speed control of devices with discrete speed sets. - Ravishankar Rao; Sarma B. K. Vrudhula (DAC, 2005)

Stochastic Power Grid Analysis Considering Process Variations. - Praveen Ghanta; Sarma B. K. Vrudhula; Rajendran Panda; Janet Meiling Wang (DATE, 2005)

Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. - Krzysztof S. Berezowski; Sarma B. K. Vrudhula (DSD, 2005)

Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (ICCAD, 2005)

Battery optimization vs energy optimization: which to choose and when? - Ravishankar Rao; Sarma B. K. Vrudhula (ICCAD, 2005)

Power balanced coverage-time optimization for clustered wireless sensor networks. - Tao Shu; Marwan Krunz; Sarma B. K. Vrudhula (MobiHoc, 2005)

Probability distribution of signal arrival times using Bayesian networks. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; David T. Blaauw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. - Sarvesh Bhardwaj; Yu Cao 001; Sarma B. K. Vrudhula (ASP-DAC, 2006)

Predictive Modeling of the NBTI Effect for Reliable Design. - Sarvesh Bhardwaj; Wenping Wang 004; Rakesh Vattikonda; Yu Cao 001; Sarma B. K. Vrudhula (CICC, 2006)

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; Praveen Ghanta; Yu Cao 001 (DAC, 2006)

High-level power management of embedded systems with application-specific energy cost functions. - Youngjin Cho; Naehyuck Chang; Chaitali Chakrabarti; Sarma B. K. Vrudhula (DAC, 2006)

Stochastic variational analysis of large power grids considering intra-die correlations. - Praveen Ghanta; Sarma B. K. Vrudhula; Sarvesh Bhardwaj; Rajendran Panda (DAC, 2006)

Extending the lifetime of fuel cell based hybrid systems. - Jianli Zhuo; Chaitali Chakrabarti; Naehyuck Chang; Sarma B. K. Vrudhula (DAC, 2006)

A framework for statistical timing analysis using non-linear delay and slew models. - Sarvesh Bhardwaj; Praveen Ghanta; Sarma B. K. Vrudhula (ICCAD, 2006)

An optimal analytical solution for processor speed control with thermal constraints. - Ravishankar Rao; Sarma B. K. Vrudhula; Chaitali Chakrabarti; Naehyuck Chang (ISLPED, 2006)

Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. - Jianli Zhuo; Chaitali Chakrabarti; Naehyuck Chang; Sarma B. K. Vrudhula (ISLPED, 2006)

LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. - Sarvesh Bhardwaj; Yu Cao 001; Sarma B. K. Vrudhula (ISQED, 2006)

Variational Interconnect Delay Metrics for Statistical Timing Analysis. - Praveen Ghanta; Sarma B. K. Vrudhula (ISQED, 2006)

Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. - Sarvesh Bhardwaj; Yu Cao 001; Sarma B. K. Vrudhula (J. Low Power Electron., 2006)

Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. - Kaviraj Chopra; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Energy-Optimal Speed Control of a Generic Device. - Ravishankar Rao; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. - Sarma B. K. Vrudhula; Janet Meiling Wang; Praveen Ghanta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks. - Tao Shu; Marwan Krunz; Sarma B. K. Vrudhula (IEEE Trans. Wirel. Commun., 2006)

Performance optimal processor throttling under thermal constraints. - Ravishankar Rao; Sarma B. K. Vrudhula (CASES, 2007)

The Impact of NBTI on the Performance of Combinational and Sequential Circuits. - Wenping Wang 004; Shengqi Yang; Sarvesh Bhardwaj; Rakesh Vattikonda; Sarma B. K. Vrudhula; Frank Liu 001; Yu Cao 001 (DAC, 2007)

Synthesis of threshold logic circuits using tree matching. - Tejaswi Gowda; Samuel Leshner; Sarma B. K. Vrudhula; Goran Konjevod (ECCTD, 2007)

Combinational equivalence checking for threshold logic circuits. - Tejaswi Gowda; Sarma B. K. Vrudhula; Goran Konjevod (ACM Great Lakes Symposium on VLSI, 2007)

Throughput of multi-core processors under thermal constraints. - Ravishankar Rao; Sarma B. K. Vrudhula; Chaitali Chakrabarti (ISLPED, 2007)

Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. - Amit Goel; Sarvesh Bhardwaj; Praveen Ghanta; Sarma B. K. Vrudhula (PATMOS, 2007)

A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (VLSI Design, 2007)

Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. - Sarma B. K. Vrudhula; Sarvesh Bhardwaj (VLSI Design, 2007)

Analysis of Power Supply Noise in the Presence of Process Variations. - Praveen Ghanta; Sarma B. K. Vrudhula (IEEE Des. Test Comput., 2007)

Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. - Krzysztof S. Berezowski; Sarma B. K. Vrudhula (J. Multiple Valued Log. Soft Comput., 2007)

Energy optimal speed control of a producer-consumer device pair. - Ravishankar Rao; Sarma B. K. Vrudhula (ACM Trans. Embed. Comput. Syst., 2007)

Decomposition based approach for synthesis of multi-level threshold logic circuits. - Tejaswi Gowda; Sarma B. K. Vrudhula (ASP-DAC, 2008)

Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. - Tejaswi Gowda; Samuel Leshner; Sarma B. K. Vrudhula; Seungchan Kim (BIODEVICES (1), 2008)

Statistical waveform and current source based standard cell models for accurate timing analysis. - Amit Goel; Sarma B. K. Vrudhula (DAC, 2008)

Current source based standard cell model for accurate signal integrity and timing analysis. - Amit Goel; Sarma B. K. Vrudhula (DATE, 2008)

Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. - Ravishankar Rao; Sarma B. K. Vrudhula (ICCAD, 2008)

Analytical results for design space exploration of multi-core processors employing thread migration. - Ravishankar Rao; Sarma B. K. Vrudhula; Krzysztof S. Berezowski (ISLPED, 2008)

A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. - Amit Goel; Sarma B. K. Vrudhula; Feroze Taraporevala; Praveen Ghanta (ISQED, 2008)

A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. - Saravanan Ramamoorthy; Haibo Wang 005; Sarma B. K. Vrudhula (ISQED, 2008)

Power Reduction of Functional Units Considering Temperature and Process Variations. - Deepa Kannan; Aviral Shrivastava; Sarvesh Bhardwaj; Sarma B. K. Vrudhula (VLSI Design, 2008)

Temperature and Process Variations Aware Power Gating of Functional Units. - Deepa Kannan; Aviral Shrivastava; Vipin Mohan; Sarvesh Bhardwaj; Sarma B. K. Vrudhula (VLSI Design, 2008)

Scalable model for predicting the effect of negative bias temperature instability for reliable design. - Sarvesh Bhardwaj; Wenping Wang 004; Rakesh Vattikonda; Yu Cao 001; Sarma B. K. Vrudhula (IET Circuits Devices Syst., 2008)

Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (J. Low Power Electron., 2008)

Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; Amit Goel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A fuel-cell-battery hybrid for portable embedded systems. - Kyungsoo Lee; Naehyuck Chang; Jianli Zhuo; Chaitali Chakrabarti; Sudheendra Kadri; Sarma B. K. Vrudhula (ACM Trans. Design Autom. Electr. Syst., 2008)

A scalable parallel H.264 decoder on the cell broadband engine architecture. - Michael A. Baker; Pravin Dalale; Karam S. Chatha; Sarma B. K. Vrudhula (CODES+ISSS, 2009)

Throughput optimal task allocation under thermal constraints for multi-core processors. - Vinay Hanumaiah; Ravishankar Rao; Sarma B. K. Vrudhula; Karam S. Chatha (DAC, 2009)

Performance optimal speed control of multi-core processors under thermal constraints. - Vinay Hanumaiah; Sarma B. K. Vrudhula; Karam S. Chatha (DATE, 2009)

Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. - Vinay Hanumaiah; Sarma B. K. Vrudhula; Karam S. Chatha (ICCAD, 2009)

Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. - Ravishankar Rao; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. - Jianli Zhuo; Chaitali Chakrabarti; Kyungsoo Lee; Naehyuck Chang; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. - Samuel Leshner; Krzysztof S. Berezowski; Xiaoyin Yao; Gayathri Chalivendra; Saurabh Patel; Sarma B. K. Vrudhula (ISVLSI, 2010)

Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. - Aviral Shrivastava; Deepa Kannan; Sarvesh Bhardwaj; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 2010)

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. - Wenping Wang 004; Shengqi Yang; Sarvesh Bhardwaj; Sarma B. K. Vrudhula; Frank Liu 001; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Reliability-aware thermal management for hard real-time applications on multi-core processors. - Vinay Hanumaiah; Sarma B. K. Vrudhula (DATE, 2011)

A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient fir filter implementation. - Gayathri Chalivendra; Vinay Hanumaiah; Sarma B. K. Vrudhula (ACM Great Lakes Symposium on VLSI, 2011)

Enabling Multithreading on CGRAs. - Aviral Shrivastava; Jared Pager; Reiley Jeyapaul; Mahdi Hamzeh; Sarma B. K. Vrudhula (ICPP, 2011)

Temperature dependent wire delay estimation in floorplanning. - Andreas Thor Winther; Wei Liu 016; Alberto Nannarelli; Sarma B. K. Vrudhula (NORCHIP, 2011)

Identification of Threshold Functions and Synthesis of Threshold Networks. - Tejaswi Gowda; Sarma B. K. Vrudhula; Niranjan Kulkarni; Krzysztof S. Berezowski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. - Vinay Hanumaiah; Sarma B. K. Vrudhula; Karam S. Chatha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

EPIMap: using epimorphism to map applications on CGRAs. - Mahdi Hamzeh; Aviral Shrivastava; Sarma B. K. Vrudhula (DAC, 2012)

Minimizing area and power of sequential CMOS circuits using threshold decomposition. - Niranjan Kulkarni; Nishant Nukala; Sarma B. K. Vrudhula (ICCAD, 2012)

Optimal range assignment in solar powered active wireless sensor networks. - Benjamin Gaudette; Vinay Hanumaiah; Sarma B. K. Vrudhula; Marwan Krunz (INFOCOM, 2012)

Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors. - Vinay Hanumaiah; Sarma B. K. Vrudhula (IEEE Trans. Computers, 2012)

REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). - Mahdi Hamzeh; Aviral Shrivastava; Sarma B. K. Vrudhula (DAC, 2013)

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. - Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Deepak Kadetotad; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Jae-sun Seo; Yu Cao 001 (BICA, 2014)

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (BioCAS, 2014)

Branch-Aware Loop Mapping on CGRAs. - Mahdi Hamzeh; Aviral Shrivastava; Sarma B. K. Vrudhula (DAC, 2014)

A fast, energy efficient, field programmable threshold-logic array. - Niranjan Kulkarni; Jinghua Yang; Sarma B. K. Vrudhula (FPT, 2014)

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. - Jinghua Yang; Niranjan Kulkarni; Shimeng Yu; Sarma B. K. Vrudhula (NANOARCH, 2014)

The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. - Zihan Xu; Matteo Cavaliere; Pei An; Sarma B. K. Vrudhula; Yu Cao 001 (Fundam. Informaticae, 2014)

Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. - Nishant Nukala; Niranjan Kulkarni; Sarma B. K. Vrudhula (J. Parallel Distributed Comput., 2014)

Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling. - Vinay Hanumaiah; Sarma B. K. Vrudhula (IEEE Trans. Computers, 2014)

STEAM: A Smart Temperature and Energy Aware Multicore Controller. - Vinay Hanumaiah; Digant Desai; Benjamin Gaudette; Carole-Jean Wu; Sarma B. K. Vrudhula (ACM Trans. Embed. Comput. Syst., 2014)

Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks. - Benjamin Gaudette; Vinay Hanumaiah; Marwan Krunz; Sarma B. K. Vrudhula (ACM Trans. Sens. Networks, 2014)

Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. - Jinghua Yang; Joseph Davis; Niranjan Kulkarni; Jae-sun Seo; Sarma B. K. Vrudhula (CICC, 2015)

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. - Pai-Yu Chen; Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (DATE, 2015)

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. - Pai-Yu Chen; Binbin Lin; I-Ting Wang; Tuo-Hung Hou; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (ICCAD, 2015)

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. - Yufei Ma 002; Minkyu Kim 001; Yu Cao 001; Jae-sun Seo; Sarma B. K. Vrudhula (ICCD, 2015)

Design of threshold logic gates using emerging devices. - Sarma B. K. Vrudhula; Niranjan Kulkarni; Jinghua Yang (ISCAS, 2015)

Fast and robust differential flipflops and their extension to multi-input threshold gates. - Jinghua Yang; Niranjan Kulkarni; Joseph Davis; Sarma B. K. Vrudhula (ISCAS, 2015)

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells. - Debayan Mahalanabis; Vineeth Bharadwaj; Hugh J. Barnaby; Sarma B. K. Vrudhula; Michael N. Kozicki (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Thermal aware floorplanning incorporating temperature dependent wire delay estimation. - Andreas Thor Winther; Wei Liu 016; Alberto Nannarelli; Sarma B. K. Vrudhula (Microprocess. Microsystems, 2015)

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. - Naveen Suda; Vikas Chandra; Ganesh Dasika; Abinash Mohanty; Yufei Ma 002; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001 (FPGA, 2016)

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. - Yufei Ma 002; Naveen Suda; Yu Cao 001; Jae-sun Seo; Sarma B. K. Vrudhula (FPL, 2016)

Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee. - Benjamin Gaudette; Carole-Jean Wu; Sarma B. K. Vrudhula (HPCA, 2016)

Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons. - Debayan Mahalanabis; M. Sivaraj; W. Chen; S. Shah; Hugh J. Barnaby; Michael N. Kozicki; Jennifer Blain Christen; Sarma B. K. Vrudhula (ISCAS, 2016)

High-performance face detection with CPU-FPGA acceleration. - Abinash Mohanty; Naveen Suda; Minkyu Kim 001; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001 (ISCAS, 2016)

Digital IP protection using threshold voltage control. - Joseph Davis; Niranjan Kulkarni; Jinghua Yang; Aykut Dengi; Sarma B. K. Vrudhula (ISQED, 2016)

Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. - Niranjan Kulkarni; Sarma B. K. Vrudhula (CoRR, 2016)

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. - Niranjan Kulkarni; Jinghua Yang; Jae-sun Seo; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. - Niranjan Kulkarni; Aykut Dengi; Sarma B. K. Vrudhula (DAC, 2017)

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (FPGA, 2017)

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (FPL, 2017)

End-to-end scalable FPGA accelerator for deep residual networks. - Yufei Ma 002; Minkyu Kim 001; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (ISCAS, 2017)

Statistical library characterization using arbitrary polynomial chaos. - Mehmet Ince; Sule Ozev; Sarma B. K. Vrudhula (LASCAS, 2017)

FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. - Ankit Wagle; Jinghua Yang; Aykut Dengi; Sarma B. K. Vrudhula (FPL, 2018)

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. - Yufei Ma 002; Tu Zheng; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (ICCAD, 2018)

DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference. - Davesh Shingari; Akhil Arunkumar; Benjamin Gaudette; Sarma B. K. Vrudhula; Carole-Jean Wu (ISPASS, 2018)

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. - Yufei Ma 002; Naveen Suda; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (Integr., 2018)

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-sun Seo (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. - Jinghua Yang; Aykut Dengi; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing. - Elham Azari; Sarma B. K. Vrudhula (IEEE BigData, 2019)

An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing. - Elham Azari; Aykut Dengi; Sarma B. K. Vrudhula (FPGA, 2019)

Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance. - Ankit Wagle; Elham Azari; Sarma B. K. Vrudhula (ICCAD, 2019)

Threshold Logic in a Flash. - Ankit Wagle; Gian Singh; Jinghua Yang; Sunil P. Khatri; Sarma B. K. Vrudhula (ICCD, 2019)

Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties. - Benjamin Gaudette; Carole-Jean Wu; Sarma B. K. Vrudhula (IEEE Trans. Mob. Comput., 2019)

Enabling Incremental Knowledge Transfer for Object Detection at the Edge. - Mohammad Farhadi; Mehdi Ghasemi 003; Sarma B. K. Vrudhula; Yezhou Yang (CVPR Workshops, 2020)

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. - Ankit Wagle; Sunil P. Khatri; Sarma B. K. Vrudhula (ICCD, 2020)

A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. - Elham Azari; Ankit Wagle; Sunil P. Khatri; Sarma B. K. Vrudhula (ISQED, 2020)

Enabling Incremental Knowledge Transfer for Object Detection at the Edge. - Mohammad Farhadi Bajestani; Mehdi Ghasemi 003; Sarma B. K. Vrudhula; Yezhou Yang (CoRR, 2020)

Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-Sun Seo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Performance Modeling for CNN Inference Accelerators on FPGA. - Yufei Ma 002; Yu Cao 001; Sarma B. K. Vrudhula; Jae-Sun Seo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. - Elham Azari; Sarma B. K. Vrudhula (ACM Trans. Embed. Comput. Syst., 2020)

CIDAN: Computing in DRAM with Artificial Neurons. - Gian Singh; Ankit Wagle; Sarma B. K. Vrudhula; Sunil P. Khatri (ICCD, 2021)

Energy-Efficient Mapping for a Network of DNN Models at the Edge. - Mehdi Ghasemi 003; Soroush Heidari; Young Geun Kim 001; Aaron Lamb; Carole-Jean Wu; Sarma B. K. Vrudhula (SMARTCOMP, 2021)

A Flash-based Current-mode IC to Realize Quantized Neural Networks. - Kyler R. Scott; Cheng-Yen Lee; Sunil P. Khatri; Sarma B. K. Vrudhula (DATE, 2022)

Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. - Ayushi Dube; Ankit Wagle; Gian Singh; Sarma B. K. Vrudhula (ICCAD, 2022)

CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs. - Soroush Heidari; Mehdi Ghasemi 003; Young Geun Kim 001; Carole-Jean Wu; Sarma B. K. Vrudhula (IEEE Trans. Computers, 2022)

Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance. - Ankit Wagle; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. - Ankit Wagle; Gian Singh; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays. - Mehdi Ghasemi 003; Daler N. Rakhmatov; Carole-Jean Wu; Sarma B. K. Vrudhula (ACM Trans. Embed. Comput. Syst., 2022)

PARAG: PIM Architecture for Real-Time Acceleration of GCNs. - Gian Singh; Sanmukh R. Kuppannagari; Sarma B. K. Vrudhula (HiPC, 2023)

A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. - Cheng-Yen Lee; Sunil P. Khatri; Sarma B. K. Vrudhula (ISQED, 2023)

Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. - Vidya A. Chhabria; Chetan Choppali Sudarshan; Sarma B. K. Vrudhula; Sachin S. Sapatnekar (CoRR, 2023)

A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. - Ankit Wagle; Jinghua Yang; Niranjan Kulkarni; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers. - Gian Singh; Sarma B. K. Vrudhula (ACM Great Lakes Symposium on VLSI, 2024)

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. - Chetan Choppali Sudarshan; Nikhil Matkar; Sarma B. K. Vrudhula; Sachin S. Sapatnekar; Vidya A. Chhabria (HPCA, 2024)

Elastic Execution of Multi-Tenant DNNs on Heterogeneous Edge MPSoCs. - Soroush Heidari; Mehdi Ghasemi 003; Young Geun Kim 001; Carole-Jean Wu; Sarma B. K. Vrudhula (SEC, 2024)

Hardware-Software Co-Design for Path Planning by Drones. - Ayushi Dube; Omkar Patil; Gian Singh; Nakul Gopalan; Sarma B. K. Vrudhula (IROS, 2024)

Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture. - Gian Singh; Ayushi Dube; Sarma B. K. Vrudhula (ISVLSI, 2024)

HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. - Gyudong Kim; Mehdi Ghasemi 003; Soroush Heidari; Seungryong Kim; Young Geun Kim 001; Sarma B. K. Vrudhula; Carole-Jean Wu (MLSys, 2024)

A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM. - Gian Singh; Ayushi Dube; Sarma B. K. Vrudhula (VLSI-SoC, 2024)

A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. - Kyler R. Scott; Cheng-Yen Lee; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. - Ankit Wagle; Gian Singh; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Energy-Efficient, Delay-Constrained Edge Computing of a Network of DNNs. - Mehdi Ghasemi 003; Soroush Heidari; Young Geun Kim 001; Carole-Jean Wu; Sarma B. K. Vrudhula (IEEE Trans. Computers, 2025)

A Scalable and Energy-Efficient Processing-in-Memory Architecture for Gen-AI. - Gian Singh; Sarma Vrudhula (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)