On the relation between wire length distributions and placement of logic on master slice ICs. - Sarma Sastry; Alice C. Parker (DAC, 1984)

Stochastic Models for Wireability Analysis of Gate Arrays. - Sarma Sastry; Alice C. Parker (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

A General Purpose VLSI Array for Efficient Signal and Image Processsing. - Viktor K. Prasanna; Sarma Sastry (ICPP, 1987)

Parallel Placement on Reduced Array Architecture. - C. P. Ravikumar; Sarma Sastry (DAC, 1988)

Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. - Sarma Sastry; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. - Sarma Sastry; Jen-I Pi (DAC, 1989)

Parallel Placement on Hypercube Architecture. - C. P. Ravikumar; Sarma Sastry (ICPP (3), 1989)

A hardware accelerator for hierarchical VLSI routing. - C. P. Ravikumar; Sarma Sastry (Integr., 1989)

Flexible Transistor Matrix (FTM). - King C. Ho; Sarma Sastry (DAC, 1991)

A Branching Process Model for Observability Analysis of Combinational Circuits. - Sarma Sastry; Amitava Majumdar 002 (DAC, 1991)

Topological via minimization and routing. - Ahsan Abdullah; Sarma Sastry (Great Lakes Symposium on VLSI, 1991)

VYUHA: A detailed router for multiple routing models. - C. P. Ravikumar; Sarma Sastry (Integr., 1991)

Test efficiency analysis of random self-test of sequential circuits. - Sarma Sastry; Amitava Majumdar 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Estimating the minimum of partitioning and floorplanning problems. - Sarma Sastry; Jen-I Pi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification. - Yung-Te Lai; Sarma Sastry (DAC, 1992)

On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. - Amitava Majumdar 002; Sarma Sastry (DAC, 1992)

Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. - Yung-Te Lai; Sarma Sastry; Massoud Pedram (ICCD, 1992)

Statistical Analysis of Controllability. - Amitava Majumdar 002; Sarma Sastry (VLSI Design, 1993)

Probabilistic characterization of controllability in general homogeneous circuits. - Amitava Majumdar 002; Sarma Sastry (Comput. Aided Des., 1993)