Estimation of signal arrival times in the presence of delay noise. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; David T. Blaauw (ICCAD, 2002)

AU: Timing Analysis Under Uncertainty. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; David T. Blaauw (ICCAD, 2003)

Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. - Kaviraj Chopra; Sarma B. K. Vrudhula; Sarvesh Bhardwaj (VLSI Design, 2004)

An efficient combinationality check technique for the synthesis of cyclic combinational circuits. - Vineet Agarwal; Navneeth Kankani; Ravishankar Rao; Sarvesh Bhardwaj; Janet Meiling Wang (ASP-DAC, 2005)

Leakage minimization of nano-scale circuits in the presence of systematic and random variations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (DAC, 2005)

Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (ICCAD, 2005)

Probability distribution of signal arrival times using Bayesian networks. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; David T. Blaauw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. - Sarvesh Bhardwaj; Yu Cao 001; Sarma B. K. Vrudhula (ASP-DAC, 2006)

Predictive Modeling of the NBTI Effect for Reliable Design. - Sarvesh Bhardwaj; Wenping Wang 004; Rakesh Vattikonda; Yu Cao 001; Sarma B. K. Vrudhula (CICC, 2006)

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; Praveen Ghanta; Yu Cao 001 (DAC, 2006)

Stochastic variational analysis of large power grids considering intra-die correlations. - Praveen Ghanta; Sarma B. K. Vrudhula; Sarvesh Bhardwaj; Rajendran Panda (DAC, 2006)

A framework for statistical timing analysis using non-linear delay and slew models. - Sarvesh Bhardwaj; Praveen Ghanta; Sarma B. K. Vrudhula (ICCAD, 2006)

LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. - Sarvesh Bhardwaj; Yu Cao 001; Sarma B. K. Vrudhula (ISQED, 2006)

Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. - Sarvesh Bhardwaj; Yu Cao 001; Sarma B. K. Vrudhula (J. Low Power Electron., 2006)

The Impact of NBTI on the Performance of Combinational and Sequential Circuits. - Wenping Wang 004; Shengqi Yang; Sarvesh Bhardwaj; Rakesh Vattikonda; Sarma B. K. Vrudhula; Frank Liu 001; Yu Cao 001 (DAC, 2007)

Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. - Amit Goel; Sarvesh Bhardwaj; Praveen Ghanta; Sarma B. K. Vrudhula (PATMOS, 2007)

A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (VLSI Design, 2007)

Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. - Sarma B. K. Vrudhula; Sarvesh Bhardwaj (VLSI Design, 2007)

Power Reduction of Functional Units Considering Temperature and Process Variations. - Deepa Kannan; Aviral Shrivastava; Sarvesh Bhardwaj; Sarma B. K. Vrudhula (VLSI Design, 2008)

Temperature and Process Variations Aware Power Gating of Functional Units. - Deepa Kannan; Aviral Shrivastava; Vipin Mohan; Sarvesh Bhardwaj; Sarma B. K. Vrudhula (VLSI Design, 2008)

Scalable model for predicting the effect of negative bias temperature instability for reliable design. - Sarvesh Bhardwaj; Wenping Wang 004; Rakesh Vattikonda; Yu Cao 001; Sarma B. K. Vrudhula (IET Circuits Devices Syst., 2008)

Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (J. Low Power Electron., 2008)

Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. - Sarvesh Bhardwaj; Sarma B. K. Vrudhula; Amit Goel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Secure and Robust Localization in a Wireless Ad Hoc Environment. - Satyajayant Misra; Guoliang Xue; Sarvesh Bhardwaj (IEEE Trans. Veh. Technol., 2009)

Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. - Aviral Shrivastava; Deepa Kannan; Sarvesh Bhardwaj; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 2010)

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. - Wenping Wang 004; Shengqi Yang; Sarvesh Bhardwaj; Sarma B. K. Vrudhula; Frank Liu 001; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

On Timing Closure: Buffer Insertion for Hold-Violation Removal. - Pei-Ci Wu; Martin D. F. Wong; Ivailo Nedelchev; Sarvesh Bhardwaj; Vidyamani Parkhe (DAC, 2014)

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. - Ankur Sharma 001; David G. Chinnery; Sarvesh Bhardwaj; Chris C. N. Chu (ICCAD, 2015)

Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. - Ankur Sharma 001; David G. Chinnery; Tiago Reimann; Sarvesh Bhardwaj; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)