A Real-Time Java System on a Multithreaded Java Microcontroller. - Matthias Pfeffer; Sascha Uhrig; Theo Ungerer; Uwe Brinkschulte (Symposium on Object-Oriented Real-Time Distributed Computing, 2002)

Hardware-based Power Management for Real-Time Applications. - Sascha Uhrig; Theo Ungerer (ISPDC, 2003)

Real-time event-handling and scheduling on a multithreaded Java microcontroller. - Jochen Kreuzinger; Uwe Brinkschulte; Matthias Pfeffer; Sascha Uhrig; Theo Ungerer (Microprocess. Microsystems, 2003)

CARUSO - Project Goals and Principal Approach. - Uwe Brinkschulte; Jürgen Becker 001; Klaus Dorfmüller-Ulhaas; Ralf König 001; Sascha Uhrig; Theo Ungerer (GI Jahrestagung (2), 2004)

Fine-grained power management for multithreaded processor cores. - Sascha Uhrig; Theo Ungerer (SAC, 2004)

Optimierung des Energieverbrauchs in echtzeitfähigen, mehrfädigen Prozessoren. - Sascha Uhrig (2004)

Energy Management for Embedded Multithreaded Processors with Integrated EDF Scheduling. - Sascha Uhrig; Theo Ungerer (ARCS, 2005)

Der mehrfädige Komodo-Mikrocontroller (The Multithreaded Komodo Microcontroller). - Uwe Brinkschulte; Sascha Uhrig; Theo Ungerer (it Inf. Technol., 2005)

Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. - Sascha Uhrig; Stefan Maier; Georgi Kuzmanov; Theo Ungerer (IPDPS, 2006)

jamuth: an IP processor core for embedded Java real-time systems. - Sascha Uhrig; Jörg Wiese (JTRES, 2007)

An IP Core for Embedded Java Systems. - Sascha Uhrig; Jörg Mische; Theo Ungerer (SAMOS, 2007)

An Operating System Architecture for Organic Computing in Embedded Real-Time Systems. - Florian Kluge; Jörg Mische; Sascha Uhrig; Theo Ungerer (ATC, 2008)

Exploiting spare resources of in-order SMT processors executing hard real-time threads. - Jörg Mische; Sascha Uhrig; Florian Kluge; Theo Ungerer (ICCD, 2008)

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors. - Stefan Metzlaff; Sascha Uhrig; Jörg Mische; Theo Ungerer (MEDEA@PACT, 2008)

A Two-Layered Management Architecture for Building Adaptive Real-Time Systems. - Florian Kluge; Sascha Uhrig; Jörg Mische; Theo Ungerer (SEUS, 2008)

A Flexible Java-on-Chip Solution (Eine flexible Java-on-Chip Lösung). - Sascha Uhrig (it Inf. Technol., 2008)

A Garbage Collection Technique for Embedded Multithreaded Multicore Processors. - Sascha Uhrig; Theo Ungerer (ARCS, 2009)

IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. - Jörg Mische; Sascha Uhrig; Florian Kluge; Theo Ungerer (HiPEAC, 2009)

Risks and chances of many-core processors. - Sascha Uhrig (HPCS, 2009)

Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC. - Sascha Uhrig (SAMOS, 2009)

Implementing AUTOSAR scheduling and resource management on an embedded SMT processor. - Florian Kluge; Chenglong Yu; Jörg Mische; Sascha Uhrig; Theo Ungerer (SCOPES, 2009)

Dynamic Workload Prediction for Soft Real-Time Applications. - Florian Kluge; Sascha Uhrig; Jörg Mische; Benjamin Satzger; Theo Ungerer (CIT, 2010)

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. - Jörg Mische; Irakli Guliashvili; Sascha Uhrig; Theo Ungerer (ARCS, 2010)

Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. - Basher Shehan; Ralf Jahr; Sascha Uhrig; Theo Ungerer (DSD, 2010)

Static Speculation as Post-link Optimization for the Grid Alu Processor. - Ralf Jahr; Basher Shehan; Sascha Uhrig; Theo Ungerer (Euro-Par Workshops, 2010)

The MANy JAva Core processor (MANJAC). - Sascha Uhrig (HPCS, 2010)

Optimisation of Energy Consumption of Soft Real-Time Applications by Workload Prediction. - Florian Kluge; Sascha Uhrig; Jörg Mische; Benjamin Satzger; Theo Ungerer (ISORC Workshops, 2010)

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor. - Julian Wolf 002; Mike Gerdes 001; Florian Kluge; Sascha Uhrig; Jörg Mische; Stefan Metzlaff; Christine Rochange; Hugues Cassé; Pascal Sainrat; Theo Ungerer (ISORC, 2010)

The embedded Java benchmark suite JemBench. - Martin Schoeberl; Thomas B. Preußer; Sascha Uhrig (JTRES, 2010)

Using SMT to Hide Context Switch Times of Large Real-Time Tasksets. - Jörg Mische; Sascha Uhrig; Florian Kluge; Theo Ungerer (RTCSA, 2010)

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. - Theo Ungerer; Francisco J. Cazorla; Pascal Sainrat; Guillem Bernat; Zlatko Petrov; Christine Rochange; Eduardo Quiñones; Mike Gerdes 001; Marco Paolieri; Julian Wolf 002; Hugues Cassé; Sascha Uhrig; et al. (IEEE Micro, 2010)

A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware. - Stefan Metzlaff; Irakli Guliashvili; Sascha Uhrig; Theo Ungerer (ARCS, 2011)

Tracing Static Fields of Embedded Parallel Java Applications. - Sascha Uhrig (COMPSAC Workshops, 2011)

A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks. - Marco Paolieri; Eduardo Quiñones; Francisco J. Cazorla; Julian Wolf 002; Theo Ungerer; Sascha Uhrig; Zlatko Petrov (ISORC, 2011)

RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor. - Julian Wolf 002; Mike Gerdes 001; Florian Kluge; Sascha Uhrig; Jörg Mische; Stefan Metzlaff; Christine Rochange; Hugues Cassé; Pascal Sainrat; Theo Ungerer (Comput. Syst. Sci. Eng., 2011)

Implementing a ring-based real-time capable network using a multithreaded Java processor. - Sascha Uhrig (JTRES, 2012)

Fine-grained timing and control flow error checking for hard real-time task execution. - Julian Wolf 002; Bernhard Fechner; Sascha Uhrig; Theo Ungerer (SIES, 2012)

Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor. - Sascha Uhrig; Ralf Jahr; Theo Ungerer (IET Comput. Digit. Tech., 2012)

parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. - Theo Ungerer; Christian Bradatsch; Mike Gerdes 001; Florian Kluge; Ralf Jahr; Jörg Mische; João Fernandes; Pavel G. Zaykov; Zlatko Petrov; Bert Böddeker; Sebastian Kehr; Hans Regler; et al. (DSD, 2013)

Performance Evaluation of the Time Analysable On-Demand Coherent Cache. - Arthur Pyka; Mathias Rohde; Sascha Uhrig (TrustCom/ISPA/IUCC, 2013)

A hard real-time capable multi-core SMT processor. - Marco Paolieri; Jörg Mische; Stefan Metzlaff; Mike Gerdes 001; Eduardo Quiñones; Sascha Uhrig; Theo Ungerer; Francisco J. Cazorla (ACM Trans. Embed. Comput. Syst., 2013)

Time-Predictable Architectures. - Christine Rochange; Sascha Uhrig; Pascal Sainrat (iSTE / Wiley, 2014)

Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems. - Arthur Pyka; Mathias Rohde; Sascha Uhrig (ICSAMOS, 2014)

A real-time capable coherent data cache for multicores. - Arthur Pyka; Mathias Rohde; Sascha Uhrig (Concurr. Comput. Pract. Exp., 2014)

MESI-Based Cache Coherence for Hard Real-Time Multicore Systems. - Sascha Uhrig; Lillian Tadros; Arthur Pyka (ARCS, 2015)

The shift to multicores in real-time and safety-critical systems. - Selma Saidi; Rolf Ernst; Sascha Uhrig; Henrik Theiling; Benoît Dupont de Dinechin (CODES+ISSS, 2015)

Case study: Performance and WCET analysis for parallelised avionic applications with ODC2. - Arthur Pyka; Pavel G. Zaykov; Hugues Cassé; Haluk Ozaktas; Christine Rochange; Sascha Uhrig (INDIN, 2015)

The EMC2 Project on Embedded Microcontrollers: Technical Progress after Two Years. - Werner Weber; Alfred Hoess; Jan van Deventer; Frank Oppenheimer; Rolf Ernst; Adam Kostrzewa; Philippe Dore; Thierry Goubier; Haris Isakovic; Norbert Druml; Egon Wuchner; Daniel Schneider 001; et al. (DSD, 2016)

Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions. - Ankit Agrawal 005; Gerhard Fohler; Jan Nowotsch; Sascha Uhrig; Michael Paulitsch (RTAS, 2016)

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. - Theo Ungerer; Christian Bradatsch; Martin Frieb; Florian Kluge; Jörg Mische; Alexander Stegmeier; Ralf Jahr; Mike Gerdes 001; Pavel G. Zaykov; Lucie Matusova; Zai Jian Jia Li; Zlatko Petrov; et al. (ACM Trans. Embed. Comput. Syst., 2016)

Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. - Ankit Agrawal 005; Gerhard Fohler; Johannes Freitag; Jan Nowotsch; Sascha Uhrig; Michael Paulitsch (ECRTS, 2017)

A scheduling framework for handling integrated modular avionic systems on multicore platforms. - Alessandra Melani; Renato Mancuso 001; Marco Caccamo; Giorgio C. Buttazzo; Johannes Freitag; Sascha Uhrig (RTCSA, 2017)

Closed Loop Controller for Multicore Real-Time Systems. - Johannes Freitag; Sascha Uhrig (ARCS, 2018)

Virtual Timing Isolation for Mixed-Criticality Systems. - Johannes Freitag; Sascha Uhrig; Theo Ungerer (ECRTS, 2018)

Safety and Security Coengineering in Embedded Systems. - Daniel Schneider 001; Jens Braband; Erwin Schoitsch; Sascha Uhrig; Stefan Katzenbeisser 001 (Secur. Commun. Networks, 2019)

Efficient and Mathematically Robust Operations for Certified Neural Networks Inference. - Fabien Geyer; Johannes Freitag; Tobias Schulz; Sascha Uhrig (CoRR, 2024)