Comparative analysis of 8 X 8 Bit Vedic and Booth Multiplier. - Sasha Garg; Swati Garg; Vidhi Sachdeva (ICACCI, 2014)

FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers. - Sasha Garg; Sumit Jagdish Darak (VDAT, 2016)