High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. - Rishan Senanayake; Namitha Liyanage; Sasindu Wijeratne; Sachille Atapattu; Kasun Athukorala; P. M. K. Tharaka; Geethan Karunaratne; R. M. A. U. Senarath; Ishantha Perera; Ashen Ekanayake; Ajith Pasqual (ASAP, 2017)

Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. - Sasindu Wijeratne; Sandaruwan Jayaweera; Mahesh Dananjaya; Ajith Pasqual (ASAP, 2018)

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. - Sasindu Wijeratne; Ashen Ekanayake; Sandaruwan Jayaweera; Danuka Ravishan; Ajith Pasqual (FPGA, 2019)

A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. - Ruizhi Zhang; Sasindu Wijeratne; Yang Yang 111; Sanmukh R. Kuppannagari; Viktor K. Prasanna (HPEC, 2020)

Programmable FPGA-based Memory Controller. - Sasindu Wijeratne; Sanket Pattnaik; Zhiyu Chen; Rajgopal Kannan; Viktor K. Prasanna (HOTI, 2021)

Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. - Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (HPEC, 2021)

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. - Sasindu Wijeratne; Sandaruwan Jayaweera; Mahesh Dananjaya; Ajith Pasqual (CoRR, 2021)

Towards Programmable Memory Controller for Tensor Decomposition. - Sasindu Wijeratne; Ta-Yang Wang; Rajgopal Kannan; Viktor K. Prasanna (DATA, 2022)

Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. - Sasindu Wijeratne; Akhilesh R. Jaiswal; Ajey P. Jacob; Bingyi Zhang; Viktor K. Prasanna (HPEC, 2022)

Modeling the Energy Efficiency of GEMM using Optical Random Access Memory. - Bingyi Zhang; Akhilesh R. Jaiswal; Clynn Mathew; Ravi Teja Lakkireddy; Ajey P. Jacob; Sasindu Wijeratne; Viktor K. Prasanna (HPEC, 2022)

Estimating the Impact of Communication Schemes for Distributed Graph Processing. - Tian Ye 002; Sanmukh R. Kuppannagari; César A. F. De Rose; Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (ISPDC, 2022)

Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. - Sasindu Wijeratne; Ta-Yang Wang; Rajgopal Kannan; Viktor K. Prasanna (FPGA, 2023)

Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. - Paul Chen; Pavan Manjunath; Sasindu Wijeratne; Bingyi Zhang; Viktor K. Prasanna (FPL, 2023)

Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. - Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (SBAC-PAD, 2023)

Graph Neural Network for Accurate and Low-complexity SAR ATR. - Bingyi Zhang; Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna; Carl E. Busart (CoRR, 2023)

Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU $ mathcal{X}_{(d)}$. - Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (IEEECONF, 2024)

Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. - Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (CF, 2024)

Predictive Performance of Photonic SRAM-Based in-Memory Computing for Tensor Decomposition. - Sasindu Wijeratne; Sugeet Sunder; Md. Abdullah-Al Kaiser; Akhilesh Jaiswal 001; Clynn Mathew; Ajey P. Jacob; Viktor K. Prasanna (HPEC, 2024)

PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images. - Sasindu Wijeratne; Bingyi Zhang; Rajgopal Kannan; Viktor K. Prasanna; Carl E. Busart (CoRR, 2024)

Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU. - Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (CoRR, 2025)

AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs. - Sasindu Wijeratne; Rajgopal Kannan; Viktor K. Prasanna (CoRR, 2025)