Macropipelining based heterogeneous multiprocessor scheduling. - Takeo Hamada; Sati Banerjee; Paul M. Chau; Ronald D. Fellman (ICASSP, 1992)

Recursive least squares problem implementation on a generalized interconnection of DSP processors. - Sati Banerjee; Paul M. Chau (ICASSP (3), 1993)

Parallel implementations of direction finding algorithms on networks of general purpose DSP processors. - Paul M. Chau; Sati Banerjee (Integr., 1993)

Macro pipelining based scheduling on high performance heterogeneous multiprocessor systems. - Sati Banerjee; Takeo Hamada; Paul M. Chau; Ronald D. Fellman (IEEE Trans. Signal Process., 1995)

Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems. - Sati Banerjee; Paul M. Chau; Ronald D. Fellman (J. VLSI Signal Process., 1995)