An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop. - Manoj Sharma; Arti Noor; Satish Chandra Tiwari; Kunwar Singh (ARTCom, 2009)

Automated transistor width optimisation algorithms for digital circuits. - Satish Chandra Tiwari; Kunwar Singh; Maneesha Gupta (Int. J. Embed. Syst., 2013)

A closed-loop ASIC design approach based on logical effort theory and artificial neural networks. - Kunwar Singh; Satish Chandra Tiwari; Maneesha Gupta (Integr., 2019)