A high performance vertical Si nanowire CMOS for ultra high density circuits. - Satish Maheshwaram; Gaurav Kaushal; S. K. Manhas (APCCAS, 2010)

Low power SRAM design for 14 nm GAA Si-nanowire technology. - Gaurav Kaushal; H. Jeong; Satish Maheshwaram; S. K. Manhas; Sudeb Dasgupta; Seong-Ook Jung (Microelectron. J., 2015)

Lateral silicon nanowire based standard cell design for higher performance. - Om. Prakash; Mohit Sharma 003; Anand Bulusu; A. K. Saxena; S. K. Manhas; Satish Maheshwaram (APCCAS, 2016)

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. - Om. Prakash; Satish Maheshwaram; Mohit Sharma 003; Anand Bulusu; A. K. Saxena; S. K. Manhas (VDAT, 2016)

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. - Satish Maheshwaram; Om. Prakash; Mohit Sharma 003; Anand Bulusu; Sanjeev Manhas (VDAT, 2017)

Resistive Calibrated Zero Temperature Coefficient Band Gap Reference (BGR). - Nikita Dindhoria; G. S. Rohit Reddy; Satish Maheshwaram (iSES, 2022)

Impact on the Performance of North Bridge I/O Peripheral Component Interconnect Express Block in Physical Design Flow Considering Two Different Synthesis Corners at below 10nm Technology Node. - Neha Karna; Jagannadha Rao Arisankula; Satish Maheshwaram (iSES, 2022)

Performance Comparison of Circular Double Gate Transistor (CDGT) with Novel Architectures for High-Performance Applications. - Kallepelli Sagar; Satish Maheshwaram (iSES, 2022)

Emerging Two Dimensional Channel Materials for MOSFETs: A Review. - Rudravaram Srikanth; Satish Maheshwaram (iSES, 2022)

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications. - Ravi Kothapally; Vadthiya Narendar; Satish Maheshwaram (Microelectron. J., 2023)

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes. - Kallepelli Sagar; Satish Maheshwaram; Vadthiya Narendar (Microelectron. J., 2023)