FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture. - Satish S. Bhairannawar; R. Rathan; K. B. Raja; K. R. Venugopal 001; Lalit M. Patnaik (CoRR, 2014)

An Efficient Reconfigurable Architecture for Fingerprint Recognition. - Satish S. Bhairannawar; K. B. Raja; K. R. Venugopal 001 (VLSI Design, 2016)

Implementation of Fingerprint Based Biometric System Using Optimized 5/3 DWT Architecture and Modified CORDIC Based FFT. - Satish S. Bhairannawar; Sayantam Sarkar; K. B. Raja; K. R. Venugopal 001 (Circuits Syst. Signal Process., 2018)

FPGA Implementation of Optimized Karhunen-Loeve Transform for Image Processing Applications. - Satish S. Bhairannawar; Sayantam Sarkar; K. B. Raja (J. Real Time Image Process., 2020)

FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing. - Sayantam Sarkar; Satish S. Bhairannawar; K. B. Raja (IET Circuits Devices Syst., 2021)

Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications. - Sayantam Sarkar; Satish S. Bhairannawar (Multidimens. Syst. Signal Process., 2021)

Computer Game-Based Telerehabilitation Platform Targeting Manual Dexterity: Exercise Is Fun. "You Are Kidding - Right?". - Sanjay Tejraj Parmar; Anuprita Kanitkar; Nariman Sepehri; Satish S. Bhairannawar; Tony Szturm (Sensors, 2021)

Efficient reconfigurable architecture to extract image features for face recognition using local binary pattern. - Sumangala Bhavikatti; Satish S. Bhairannawar (Soft Comput., 2025)