Modified Stability Checking for On-line Error Detection. - Satish Yada; Bharadwaj S. Amrutur; Rubin A. Parekhji (VLSI Design, 2007)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. - Praveen Salihundam; Mohammed Asadullah Khan; Shailendra Jain; Yatin Vasant Hoskote; Satish Yada; Shasi Kumar; Vasantha Erraguntla; Sriram R. Vangal; Nitin Borkar (VLSI Design, 2012)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. - Vinayak Honkote; Dileep Kurian; Sriram Muthukumar; Dibyendu Ghosh; Satish Yada; Kartik Jain; Bradley Jackson; Ilya Klotchkov; Mallikarjuna Rao Nimmagadda; Shreela Dattawadkar; Pranjali Deshmukh; Ankit Gupta 011; et al. (ISSCC, 2019)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. - Ragh Kuttappa; Baris Taskin; Vinayak Honkote; Satish Yada; Jainaveen Sundaram; Dileep Kurian; Tanay Karnik; Anuradha Srinivasan (ISCAS, 2022)

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. - Srivatsa Rangachar Srinivasa; Jainaveen Sundaram Priya; Dileep Kurian; Erika Ramirez Lozano; Satish Yada; Saransh Chhabra; Kamakhya Prasad Sahu; Paolo A. Aseron; Ronald Kalim; Anuradha Srinivasan; Tanay Karnik (ISQED, 2022)

A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. - Vinayak Honkote; Ragh Kuttappa; Jainaveen Sundaram; Satish Yada; Chinnusamy Kalimuthu; Juhi Patil; Richard Lee; Cristan Paulino; Paolo A. Aseron; Trang Nguyen; Amreesh Rao; Dileep Kurian; et al. (VLSI Technology and Circuits, 2024)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)