A memory controller that reduces latency of cached SDRAM. - Seiji Miura; Satoru Akiyama (ISCAS (5), 2005)

The Umbrella Cell: A High-Density 2T Cell for SOC Applications. - Satoru Akiyama; Takao Watanabe; Nobuhiro Oodaira; Tsuyoshi Ishikawa; Digh Hisamoto (IEICE Trans. Electron., 2005)

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. - Satoru Akiyama; Tomonori Sekiguchi; Kazuhiko Kajigaya; Satoru Hanzawa; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. - Satoru Akiyama; Tomonori Sekiguchi; Riichiro Takemura; Akira Kotabe; Kiyoo Itoh 001 (ISSCC, 2009)

0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays. - Akira Kotabe; Yoshimitsu Yanagawa; Satoru Akiyama; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2010)

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. - Satoru Akiyama; Riichiro Takemura; Tomonori Sekiguchi; Akira Kotabe; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)