A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Tomonori Sekiguchi; Takayuki Kawahara (ICC, 2005)

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2005)

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. - Satoru Akiyama; Tomonori Sekiguchi; Kazuhiko Kajigaya; Satoru Hanzawa; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. - Satoru Hanzawa; Naoki Kitai; Kenichi Osada; Akira Kotabe; Yuichi Matsui; Nozomu Matsuzaki; Norikatsu Takaura; Masahiro Moniwa; Takayuki Kawahara (ISSCC, 2007)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)

Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device. - Satoru Hanzawa; Takahiro Hanyu (IEICE Trans. Electron., 2011)

Session 25 overview: Non-volatile memory solutions: Memory subcommittee. - Tadaaki Yamauchi; Satoru Hanzawa (ISSCC, 2012)