A 32-bank 256-Mb DRAM with cache and TAG. - Satoru Tanoi; Yasuhiro Tanaka; Tetsuya Tanabe; Akio Eta; Toshio Inada; Ryoji Hamazaki; Yoshio Ohtsuki; Masaru Uesugi (IEEE J. Solid State Circuits, 1994)

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. - Satoru Tanoi; Tetsuya Tanabe; Kazuhiko Takahashi; Sanpei Miyamoto; Masaru Uesugi (IEEE J. Solid State Circuits, 1996)

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. - Satoru Tanoi; Yasuhiro Tokunaga; Tetsuya Tanabe; Kazuhiko Takahashi; Atsuhiko Okada; Masahiro Itoh; Yoshiki Nagatomo; Yoshio Ohtsuki; Masaru Uesugi (IEEE J. Solid State Circuits, 1997)

BIST: required for embedded DRAM. - Satoru Tanoi (ITC, 1998)

RF-CMOS Implementation of UWB Transceivers and Its Application to Video Transmission. - Akifumi Kasamatsu; Akio Tanaka; Hiroshi Kodama; Satoru Tanoi; Yasuhiro Kaizaki; Juichi Nakada; Masami Hagio; Yoshiaki Kuraishi; Keren Li; Hitoshi Utagawa; Toshiaki Matsui; Ryuji Kohno (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. - Norifumi Kanemaru; Sho Ikeda; Tatsuya Kamimura; Sang-yeop Lee; Satoru Tanoi; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ISOCC, 2011)

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. - Sang-yeop Lee; Hiroyuki Ito; Satoru Tanoi; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2012)

A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. - Sang-yeop Lee; Norifumi Kanemaru; Sho Ikeda; Tatsuya Kamimura; Satoru Tanoi; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (IEICE Trans. Electron., 2012)

A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. - Satoru Tanoi; Tetsuo Endoh (IEICE Trans. Electron., 2014)

A 76-Gbit/s 265-GHz CMOS Receiver. - Shinsuke Hara; Ruibing Dong; Sangyeop Lee; Kyoya Takano; Naoya Toshida; Satoru Tanoi; Tatsuo Hagino; Mohamed H. Mubarak; Norihiko Sekine; Issei Watanabe; Akifumi Kasamatsu; Kunio Sakakibara; et al. (A-SSCC, 2021)

A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs. - Shunichi Kubo; Yuji Gendai; Satoshi Miura; Shinsuke Hara; Satoru Tanoi; Akifumi Kasarnatsu; Takeshi Yoshida; Satoshi Tanaka; Shuhei Arnakawa; Minoru Fujishlrna (CICC, 2024)