A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. - Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (DAC, 2011)

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. - Tadashi Yasufuku; Satoshi Iida; Hiroshi Fuketa; Koji Hirairi; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2011)

A Face-Like Structure Detection on Planet and Satellite Surfaces Using Image Processing. - Kazutaka Kurihara; Masakazu Takasu; Kazuhiro Sasao; Hal Seki; Takayuki Narabu; Mitsuo Yamamoto; Satoshi Iida; Hiroyuki Yamamoto (Advances in Computer Entertainment, 2013)

Use of "Web Map Image" and copyright act. - Nobusuke Iwasaki; Satoshi Iida (CoRR, 2018)