Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. - Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 1998)

Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. - Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (Great Lakes Symposium on VLSI, 1999)

Field modifiable architecture with FPGAs and its design methodology. - Satoshi Komatsu; Yoshihisa Kojima; Hiroshi Saito; Kenshu Seto; Masahiro Fujita (FPT, 2002)

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. - Yoshihisa Kojima; Hiroshi Saito; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (IWLS, 2002)

Irredundant address bus encoding techniques based on adaptive codebooks for low power. - Satoshi Komatsu; Masahiro Fujita (ASP-DAC, 2003)

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. - Masahiro Fujita; Satoshi Komatsu; Hiroshi Saito; Kenshu Seto; Thanyapat Sakunkonchak; Yoshihisa Kojima (HICSS, 2003)

Engineering Changes in Field Modifiable Architectures. - Hiroshi Saito; Kenshu Seto; Yoshihisa Kojima; Satoshi Komatsu; Masahiro Fujita (MEMOCODE, 2003)

Comparative Study On Verilog-Based And C-Based Hardware Design Education. - Tohru Ishihara; Satoshi Komatsu; Makoto Ikeda; Masahiro Fujita; Kunihiro Asada (MSE, 2003)

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks. - Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams. - Thanyapat Sakunkonchak; Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

AMS Extensions for Timed/Untimed System-Level Design Language. - Yu Liu; Satoshi Komatsu; Masahiro Fujita (FDL, 2005)

Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. - Shanghua Gao; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (FPT, 2005)

System level design language extensions for timed/untimed digital-analog combined system design. - Yu Liu; Thanyapat Sakunkonchak; Satoshi Komatsu; Masahiro Fujita (ACM Great Lakes Symposium on VLSI, 2005)

Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. - Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Dynamically reconfigurable protocol transducer. - Shota Watanabe; Yuji Ishikawa; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (FPT, 2006)

An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. - Satoshi Komatsu; Masahiro Fujita (ISCAS, 2006)

Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. - Yu Liu; Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

The AMS Extension to System Level Design Language - SpecC. - Yu Liu; Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Synchronization Verification in System-Level Design with ILP Solvers. - Thanyapat Sakunkonchak; Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Protocol Transducer Synthesis using Divide and Conquer approach. - Shigeru Watanabe; Kenshu Seto; Yuji Ishikawa; Satoshi Komatsu; Masahiro Fujita (ASP-DAC, 2007)

Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. - Thanyapat Sakunkonchak; Satoshi Komatsu; Masahiro Fujita (ATVA, 2007)

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. - Shanghua Gao; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (IESS, 2007)

VLSI CAD Education and Exercise Course with Public Domain Tools. - Satoshi Komatsu; Kazuyoshi Takagi; Masahiro Fujita; Kunihiro Asada (MSE, 2007)

Targeting Leakage Constraints during ATPG. - Görschwin Fey; Satoshi Komatsu; Yasuo Furukawa; Masahiro Fujita (ATS, 2008)

VLSI Test Exercise Courses for Students in EE Department. - Satoshi Komatsu (ITC, 2008)

SAT-based ATPG testing of inter- and intra-gate bridging faults. - Toru Nakura; Yutaro Tatemura; Görschwin Fey; Makoto Ikeda; Satoshi Komatsu; Kunihiro Asada (ECCTD, 2009)

Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. - Mohamed Abbas; Kwang-Ting Cheng; Yasuo Furukawa; Satoshi Komatsu; Kunihiro Asada (ETS, 2009)

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. - Shanghua Gao; Hiroaki Yoshida; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. - Mohamed Abbas; Kwang-Ting Cheng; Yasuo Furukawa; Satoshi Komatsu; Kunihiro Asada (DATE, 2010)

Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. - Mohamed Abbas; Takahiro J. Yamaguchi; Yasuo Furukawa; Satoshi Komatsu; Kunihiro Asada (ICECS, 2011)

An equivalent-time and clocked approach for continuous-time quantization. - Takahiro J. Yamaguchi; Mohamed Abbas; Mani Soma; Takafumi Aoki; Yasuo Furukawa; Katsuhiko Degawa; Satoshi Komatsu; Kunihiro Asada (ISCAS, 2011)

Application of a continuous-time level crossing quantization method for timing noise measurements. - Takahiro J. Yamaguchi; Mani Soma; Takafumi Aoki; Yasuo Furukawa; Katsuhiko Degawa; Kunihiro Asada; Mohamed Abbas; Satoshi Komatsu (ITC, 2011)

A New Procedure for Measuring High-Accuracy Probability Density Functions. - Takahiro J. Yamaguchi; Kunihiro Asada; Kiichi Niitsu; Mohamed Abbas; Satoshi Komatsu; Haruo Kobayashi 001; Jose A. Moreira (Asian Test Symposium, 2012)

Power integrity control of ATE for emulating power supply fluctuations on customer environment. - Masahiro Ishida; Toru Nakura; Toshiyuki Kikkawa; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (ITC, 2012)

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. - Rimon Ikeno; Takashi Maruyama; Tetsuya Iizuka; Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2013)

A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. - James S. Tandon; Takahiro J. Yamaguchi; Satoshi Komatsu; Kunihiro Asada (CICC, 2013)

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISPD, 2013)

A novel test structure for measuring the threshold voltage variance in MOSFETs. - Takahiro J. Yamaguchi; James S. Tandon; Satoshi Komatsu; Kunihiro Asada (ITC, 2013)

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. - Takahiro J. Yamaguchi; James S. Tandon; Satoshi Komatsu; Kunihiro Asada (ATS, 2014)

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. - James S. Tandon; Takahiro J. Yamaguchi; Satoshi Komatsu; Kunihiro Asada (ISCAS, 2014)

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. - Masahiro Ishida; Takashi Kusaka; Toru Nakura; Satoshi Komatsu; Kunihiro Asada (ITC, 2014)

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. - Satoshi Komatsu; Takahiro J. Yamaguchi; Mohamed Abbas; Nguyen Ngoc Mai Khanh; James S. Tandon; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. - James S. Tandon; Satoshi Komatsu; Takahiro J. Yamaguchi; Kunihiro Asada (NEWCAS, 2016)

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (J. Electron. Test., 2016)

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (IEICE Trans. Electron., 2016)

A low-voltage hysteresis comparator for low power applications. - Takumi Saito; Satoshi Komatsu (ICECS, 2017)

Characteristics optimization of stochastic ADC and its automatic generation system. - Ryosuke Yumoto; Satoshi Komatsu (NEWCAS, 2017)

A Framework for Automatic Generation of Fully Synthesizable ADPLL. - Shinya Ubukata; Satoshi Komatsu (ICECS, 2018)

A PVT Variation Dependencies of VCO in Frequency Locked Loop. - Kota Hara; Satoshi Komatsu (ICECS, 2023)

A Low Power ΔΣ Modulator with Low Voltage OTA for Wearable Applications. - Naoya Maruyama; Satoshi Komatsu (ICM, 2024)