Accurate analysis of substrate sensitivity of active transistors in an analog circuit. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (ISQED, 2011)

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. - Masaaki Souda; Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2012)

Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. - Satoshi Takaya; Makoto Nagata; Hiroaki Ikeda (3DIC, 2013)

A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. - Satoshi Takaya; Makoto Nagata; Atsushi Sakai; Takashi Kariya; Shiro Uchiyama; Harufumi Kobayashi; Hiroaki Ikeda (ISSCC, 2013)

Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2013)

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. - Noriyuki Miura; Shiro Dosho; Satoshi Takaya; Daisuke Fujimoto; Takuya Kiriyama; Hiroyuki Tezuka; Takuji Miki; Hiroto Yanagawa; Makoto Nagata (ISSCC, 2014)

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking. - Satoshi Takaya; Hiroaki Ikeda; Makoto Nagata (IEICE Trans. Electron., 2014)

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. - Hiroki Noguchi; Kazutaka Ikegami; Keiichi Kushida; Keiko Abe; Shogo Itai; Satoshi Takaya; Naoharu Shimomura; Junichi Ito; Atsushi Kawasumi; Hiroyuki Hara; Shinobu Fujita (ISSCC, 2015)

In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking. - Makoto Nagata; Satoshi Takaya; Hiroaki Ikeda (IEEE Des. Test, 2015)

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. - Hiroki Noguchi; Kazutaka Ikegami; Satoshi Takaya; Eishi Arima; Keiichi Kushida; Atsushi Kawasumi; Hiroyuki Hara; Keiko Abe; Naoharu Shimomura; Junichi Ito; Shinobu Fujita; Takashi Nakada; et al. (ISSCC, 2016)

Physically Unclonable Function using Initial Waveform of Ring Oscillators. - Tetsufumi Tanamoto; Shinichi Yasuda; Satoshi Takaya; Shinobu Fujita (CoRR, 2016)

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. - Tetsufumi Tanamoto; Satoshi Takaya; Nobuaki Sakamoto; Hirotsugu Kasho; Shinichi Yasuda; Takao Marukame; Shinobu Fujita; Yuichiro Mitani (CoRR, 2017)

Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. - Tetsufumi Tanamoto; Shinichi Yasuda; Satoshi Takaya; Shinobu Fujita (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. - Takao Marukame; Kumiko Nomura; Mari Matusmoto; Satoshi Takaya; Yoshifumi Nishi (ISCAS, 2018)

SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. - Tetsufumi Tanamoto; Chika Tanaka; Satoshi Takaya; Masato Koyama (IEICE Electron. Express, 2018)

Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. - Shinobu Fujita; Satoshi Takaya; Susumu Takeda; Kazutaka Ikegami (VLSI Circuits, 2019)

18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics. - Satoshi Takaya; Hiroaki Ishihara; Kohei Onizuka (ISSCC, 2020)