Scheduling Trees onto Hypercubes and Grids Is NP-complete. - Satoshi Tayu (COCOON, 1999)

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. - Koji Ohashi; Mineo Kaneko; Satoshi Tayu (ICCD, 2000)

Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications. - Mineo Kaneko; Yoshitaka Nishio; Satoshi Tayu (ISCAS, 2000)

An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays. - Satoshi Tayu; Motoyasu Katsura; Mineo Kaneko (ISPAN, 2000)

Characterization and computation of Steiner wiring based on Elmore's delay model. - Satoshi Tayu; Mineo Kaneko (APCCAS (2), 2002)

3D scheduling based on code space exploration for dynamically reconfigurable systems. - Mineo Kaneko; Jun'ichi Yokoyama; Satoshi Tayu (ISCAS (5), 2002)

Scheduling Trees onto Hypercubes and Grids. - Satoshi Tayu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Characterization and Computation of Steiner Routing Based on Elmore's Delay Model. - Satoshi Tayu; Mineo Kaneko (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints. - Satoshi Tayu (ASP-DAC, 2003)

On the three-dimensional channel routing. - Satoshi Tayu; Patrik Hurtig; Yoshiyasu Horikawa; Shuichi Ueno (ISCAS (1), 2005)

On the Orthogonal Drawing of Outerplanar Graphs. - Kumiko Nomura; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

On the Complexity of Three-Dimensional Channel Routing (Extended Abstract). - Satoshi Tayu; Shuichi Ueno (ISCAS, 2007)

On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract). - Satoshi Tayu; Kumiko Nomura; Shuichi Ueno (ISCAS, 2008)

On Fault Testing for Reversible Circuits. - Satoshi Tayu; Shigeru Ito; Shuichi Ueno (IEICE Trans. Inf. Syst., 2008)

Cost-Constrained Minimum-Delay Multicasting. - Satoshi Tayu; Turki Ghazi Al-Mutairi; Shuichi Ueno (J. Interconnect. Networks, 2008)

Orthogonal Ray Graphs and Nano-PLA Design. - Anish Man Singh Shrestha; Satoshi Tayu; Shuichi Ueno (ISCAS, 2009)

On the Three-dimensional Orthogonal Drawing of Outerplanar Graphs. - Satoshi Tayu; Takuya Oshima; Shuichi Ueno (ISCAS, 2009)

On the two-dimensional orthogonal drawing of series-parallel graphs. - Satoshi Tayu; Kumiko Nomura; Shuichi Ueno (Discret. Appl. Math., 2009)

Universal Test Sets for Reversible Circuits. - Satoshi Tayu; Shota Fukuyama; Shuichi Ueno (COCOON, 2010)

On two-directional orthogonal ray graphs. - Anish Man Singh Shrestha; Satoshi Tayu; Shuichi Ueno (ISCAS, 2010)

On orthogonal ray graphs. - Anish Man Singh Shrestha; Satoshi Tayu; Shuichi Ueno (Discret. Appl. Math., 2010)

On Two Problems of Nano-PLA Design. - Anish Man Singh Shrestha; Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Inf. Syst., 2011)

On Minimum Feedback Vertex Sets in Graphs. - Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (ICNC, 2012)

Bandwidth of convex bipartite graphs and related graphs. - Anish Man Singh Shrestha; Satoshi Tayu; Shuichi Ueno (Inf. Process. Lett., 2012)

On Minimum Feedback Vertex Sets in Bipartite Graphs and Degree-Constraint Graphs. - Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Inf. Syst., 2013)

A note on the energy-aware mapping for NoCs. - Satoshi Tayu; Shuichi Ueno (APCCAS, 2014)

Weighted dominating sets and induced matchings in orthogonal ray graphs. - Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (CoDIT, 2014)

Dominating Sets and Induced Matchings in Orthogonal Ray Graphs. - Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Inf. Syst., 2014)

On Evasion Games on Graphs. - Satoshi Tayu; Shuichi Ueno (JCDCGG, 2015)

A Note on Harmonious Coloring of Caterpillars. - Asahi Takaoka; Shingo Okuma; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Inf. Syst., 2015)

OBDD Representation of Intersection Graphs. - Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Inf. Syst., 2015)

Dominating Sets in Two-Directional Orthogonal Ray Graphs. - Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Inf. Syst., 2015)

On orthogonal ray trees. - Irina Mustata; Kousuke Nishikawa; Asahi Takaoka; Satoshi Tayu; Shuichi Ueno (Discret. Appl. Math., 2016)

On the Three-Dimensional Channel Routing. - Satoshi Tayu; Toshihiko Takahashi; Eita Kobayashi; Shuichi Ueno (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Stable Matchings in Trees. - Satoshi Tayu; Shuichi Ueno (COCOON, 2017)

Two-layer Bottleneck Channel Track Assignment for Analog VLSI. - Kazuya Taniguchi; Satoshi Tayu; Atsushi Takahashi 001; Mathieu Molongo; Makoto Minami; Katsuya Nishioka (IPSJ Trans. Syst. LSI Des. Methodol., 2024)

A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP. - Kazuya Taniguchi; Satoshi Tayu; Atsushi Takahashi 001; Mathieu Molongo; Makoto Minami; Katsuya Nishioka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)