Information Theoretic Analysis of Connection Structure from Spike Trains. - Satoru Shiono; Satoshi Yamada; Michio Nakashima; Kenji Matsumoto (NIPS, 1992)

448-Detector optical recording system: development and application to Aplysia gill-withdrawal reflex. - Michio Nakashima; Satoshi Yamada; Satoru Shiono; Mitsuo Maeda; Fumihide Satoh (IEEE Trans. Biomed. Eng., 1992)

Information theoretic analysis of action potential trains. - Satoshi Yamada; Michio Nakashima; Kenji Matsumoto; Satoru Shiono (Biol. Cybern., 1993)

Hybrid Reinforcement Learning and Its Application to Biped Robot Control. - Satoshi Yamada; Akira Watanabe; Michio Nakashima (NIPS, 1997)

Reinforcement learning to train a cooperative network with both discrete and continuous output neurons. - Satoshi Yamada; Michio Nakashima; Satoru Shiono (IEEE Trans. Neural Networks, 1998)

Text Summarization based on Hanning Window and Dependency Strucuture Analysis. - Tsutomu Hirao; Mamiko Hatayama; Satoshi Yamada; Kazuhiro Takeuchi (NTCIR, 2001)

Neuron classification based on temporal firing patterns by the dynamical analysis with changing time resolution (DCT) method. - Ken-ichi Oshio; Satoshi Yamada; Michio Nakashima (Biol. Cybern., 2003)

Impact of Wrapped System Call Mechanism on Commodity Processors. - Satoshi Yamada; Shigeru Kusakabe; Hideo Taniguchi (ICSOFT (Selected Papers), 2006)

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology. - Hiroyuki Nakamoto; Daisuke Yamazaki; Takuji Yamamoto; Hajime Kurata; Satoshi Yamada; Kenji Mukaida; Tsuzumi Ninomiya; Takashi Ohkawa; Shoichi Masui; Kunihiko Gotoh (ISSCC, 2006)

OS Mechanism for Continuation-based Fine-grained Threads on Dedicated and Commodity Processors. - Shigeru Kusakabe; Satoshi Yamada; Mitsuhiro Aono; Masaaki Izumi; Satoshi Amamiya; Yoshinari Nomura; Hideo Taniguchi; Makoto Amamiya (IPDPS, 2007)

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology. - Hiroyuki Nakamoto; Daisuke Yamazaki; Takuji Yamamoto; Hajime Kurata; Satoshi Yamada; Kenji Mukaida; Tsuzumi Ninomiya; Takashi Ohkawa; Shoichi Masui; Kunihiko Gotoh (IEEE J. Solid State Circuits, 2007)

Effect of context aware scheduler on TLB. - Satoshi Yamada; Shigeru Kusakabe (IPDPS, 2008)

Proposal and Evaluation of APIs for Utilizing Inter-Core Time Aggregation Scheduler. - Satoshi Yamada; Shigeru Kusakabe (JSSPP, 2010)

Development of an Intelligent Dialogue Agent with Smart Devices for Older Adults: A Preliminary Study. - Satoshi Yamada; Daisuke Kitakoshi; Akihiro Yamashita; Kentarou Suzuki; Masato Suzuki (TAAI, 2018)

9.6 A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor. - Ryoji Eki; Satoshi Yamada; Hiroyuki Ozawa; Hitoshi Kai; Kazuyuki Okuike; Hareesh Gowtham; Hidetomo Nakanishi; Edan Almog; Yoel Livne; Gadi Yuval; Eli Zyss; Takashi Izawa (ISSCC, 2021)

Sequential Estimation of Prices of Newly Built Houses in Tokyo Using the Linear State Space Model. - Satoshi Yamada; Kazushi Okamoto; Atsushi Shibata (SCIS/ISIS, 2022)

Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout. - Dan Yao; Xuanyan Bai; Shogo Katayama; Anna Kuwana; Kazuyuki Kawauchi; Haruo Kobayashi 001; Kouji Hirai; Akira Suzuki; Satoshi Yamada; Tomoyuki Kato; Ritsuko Kitakoga; Takeshi Shimamura; et al. (IEICE Electron. Express, 2022)

Evaluation of Lower-Limb Kinematics during Timed Up and Go (TUG) Test in Subjects with Locomotive Syndrome (LS) Using Wearable Gait Sensors (H-Gait System). - Yoshiaki Kataoka; Yuki Saito 006; Ryo Takeda; Tomoya Ishida; Shigeru Tadano; Teppei Suzuki; Kentaro Nakamura; Akimi Nakata; Satoshi Osuka; Satoshi Yamada; Mina Samukawa; Harukazu Tohyama (Sensors, 2023)

Validity of Wearable Gait Analysis System for Measuring Lower-Limb Kinematics during Timed Up and Go Test. - Yoshiaki Kataoka; Tomoya Ishida; Satoshi Osuka; Ryo Takeda; Shigeru Tadano; Satoshi Yamada; Harukazu Tohyama (Sensors, 2024)