Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile. - Satya K. Vendra; Malgorzata Chrzanowska-Jeske (ISCAS, 2018)

Fast Thermal Goodness Evaluation of a 3D-IC Floorplan. - Satya K. Vendra; Malgorzata Chrzanowska-Jeske (ISQED, 2021)

Fast Buffer Count Estimation in 3D IC Floorplanning. - Sucheta Mohapatra; Satya K. Vendra; Malgorzata Chrzanowska-Jeske (IEEE Trans. Circuits Syst. II Express Briefs, 2021)