A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (ATS, 2015)

Enabling LOS delay test with slow scan enable. - Satyadev Ahlawat; Darshit Vaghani; Rohini Gulve; Virendra Singh (EWDTS, 2016)

A high performance scan flip-flop design for serial and mixed mode scan test. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (IOLTS, 2016)

On minimization of test power through modified scan flip-flop. - Satyadev Ahlawat; Jaynarayan T. Tudu (VDAT, 2016)

Guided shifting of test pattern to minimize test time in serial scan. - Jaynarayan T. Tudu; Satyadev Ahlawat (VDAT, 2016)

On Securing Scan Design from Scan-Based Side-Channel Attacks. - Satyadev Ahlawat; Darshit Vaghani; Jaynarayan T. Tudu; Virendra Singh (ATS, 2017)

Preventing scan-based side-channel attacks through key masking. - Satyadev Ahlawat; Darshit Vaghani; Virendra Singh (DFT, 2017)

An efficient test technique to prevent scan-based side-channel attacks. - Satyadev Ahlawat; Darshit Vaghani; Virendra Singh (ETS, 2017)

A low cost technique for scan chain diagnosis. - Satyadev Ahlawat; Darshit Vaghani; Rohini Gulve; Virendra Singh (ISCAS, 2017)

A Cost Effective Technique for Diagnosis of Scan Chain Faults. - Satyadev Ahlawat; Darshit Vaghani; Jaynarayan T. Tudu; Ashok Suhag (VDAT, 2017)

Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. - Satyadev Ahlawat; Darshit Vaghani; Naveen Bazard; Virendra Singh (EWDTS, 2018)

In-situ Monitoring for Slack Time Violation Without Performance Penalty. - Nihar Hage; Satyadev Ahlawat; Virendra Singh (ISCAS, 2018)

On Securing Scan Design Through Test Vector Encryption. - Darshit Vaghani; Satyadev Ahlawat; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (ISCAS, 2018)

Preventing Scan Attack through Test Response Encryption. - Satyadev Ahlawat; Jaynarayan T. Tudu; Manoj Singh Gaur; Masahiro Fujita; Virendra Singh (DFT, 2019)

Securing Scan through Plain-text Restriction. - Satyadev Ahlawat; Kailash Ahirwar; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (IOLTS, 2019)

A Framework for Configurable Joint-Scan Design-for-Test Architecture. - Jaynarayan T. Tudu; Satyadev Ahlawat; Sonali Shukla; Virendra Singh (J. Electron. Test., 2021)

A New Access Protocol for Elevating the Security of IJTAG Network. - Gaurav Kumar; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (ATS, 2022)

Evaluating Security of New Locking SIB-based Architectures. - Yogendra Sao; Anjum Riaz; Satyadev Ahlawat; Sk Subidh Ali (ETS, 2022)

On Attacking Locking SIB based IJTAG Architecture. - Gaurav Kumar; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (ACM Great Lakes Symposium on VLSI, 2022)

On Attacking IJTAG Architecture based on Locking SIB with Security LFSR. - Gaurav Kumar; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (IOLTS, 2022)

On Protecting IJTAG from Data Sniffing and Alteration Attacks. - Anjum Riaz; Gaurav Kumar; Jaynarayan T. Tudu; Satyadev Ahlawat (ISVLSI, 2022)

Low Cost Implementation of Deep Neural Network on Hardware. - Gaurav Kumar; Anuj Kumar; Satyadev Ahlawat; Yamuna Prasad (VDAT, 2022)

Power Analysis Attack on Locking SIB based IJTAG Achitecture. - Gaurav Kumar; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (VLSI-SoC, 2022)

On Enhancing the Security of Streaming Scan Network Architecture. - Gaurav Kumar; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (ATS, 2023)

On Evaluating the Security of Dynamic Scan Obfuscation Scheme. - Gaurav Kumar; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (IOLTS, 2023)

TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. - Aditi Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh (SOSE, 2023)

On Protecting IJTAG using an Inherently Secure SIB. - Anjum Riaz; Gaurav Kumar; Pardeep Kumar; Yamuna Prasad; Satyadev Ahlawat (VLSI-SoC, 2023)

Enhancing the Security of IJTAG Network Using Inherently Secure SIB. - Anjum Riaz; Gaurav Kumar; Pardeep Kumar; Yamuna Prasad; Satyadev Ahlawat (VLSI-SoC (Selected Papers), 2023)

On Evaluating Test Response Obfuscation and Encryption Countermeasures. - Gaurav Kumar; Anjum Riaz; Pardeep Kumar; Yamuna Prasad; Satyadev Ahlawat (IOLTS, 2024)

On Exploring Non-negative Matrix Factorization for Deep Neural Network Compression. - Mahendra Kumar Gurve; Gaurav Kumar; Sankar Behera; Yamuna Prasad; Satyadev Ahlawat (ISOCC, 2024)

MisGUIDE : Defense Against Data-Free Deep Learning Model Extraction. - Mahendra Kumar Gurve; Sankar Behera; Satyadev Ahlawat; Yamuna Prasad (CoRR, 2024)

DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. - Aditi Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh; Adnan M. Abu-Mahfouz (Pattern Recognit. Lett., 2024)

A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. - Aditi Gupta; Sukanya Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh (Clust. Comput., 2024)

KGFakeNet: A Knowledge Graph-Enhanced Model for Fake News Detection. - Anuj Kumar; Pardeep Kumar; Abhishek Yadav; Satyadev Ahlawat; Yamuna Prasad (COLING Workshops, 2025)

Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework. - Gaurav Kumar; Ashfaq Hussain Shaik; Anjum Riaz; Yamuna Prasad; Satyadev Ahlawat (DATE, 2025)

On Enhancing Code-Mixed Sentiment and Emotion Classification Using FNet and FastFormer. - Anuj Kumar; Amit Pandey; Satyadev Ahlawat; Yamuna Prasad (ICAART (3), 2025)

Approximating Nonlinear Activation Function Using Genetic Programming. - Mahendra Kumar Gurve; Gaurav Kumar; Anuj Kumar; Satyadev Ahlawat; Yamuna Prasad (ISCAS, 2025)

On Securing SSN Architecture using Test Vector Encryption. - Anjum Riaz; Pardeep Kumar; Yamuna Prasad; Satyadev Ahlawat (ISCAS, 2025)

A New Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits. - Anjum Riaz; Gaurav Kumar; Yamuna Prasad; Satyadev Ahlawat; Virendra Singh (ISCAS, 2025)

Poster Abstract: SRAM PUF-Based Logic Locking for Secure Authentication and IP Protection. - Chandranshu Gupta; Gaurav Kumar; Manish Kumar Gupta; Satyadev Ahlawat; Gaurav Varshney (SenSys, 2025)

B-CAVE: A Robust Online Time Series Change Point Detection Algorithm Based on the Between-Class Average and Variance Evaluation Approach. - Aditi Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh (IEEE Trans. Knowl. Data Eng., 2025)