Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms. - Vaddi Chandra Sekhar; Satyajit Bora; Monalisa Dash; Manchi Pavan Kumar; S. Josephine; Roy Paily (VLSID, 2016)

An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform. - Soham Talukder; Rajan Singh; Satyajit Bora; Roy Paily (Circuits Syst. Signal Process., 2020)

A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. - Satyajit Bora; Roy Paily (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers. - Satyajit Bora; Roy Paily (Circuits Syst. Signal Process., 2022)

Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures. - Titu Mary Ignatius; Satyajit Bora; Roy Paily Palathinkal (MCSoC, 2024)