Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. - Satyamurthy Pullela; Noel Menezes; Lawrence T. Pillage (DAC, 1993)

RC interconnect synthesis-a moment fitting approach. - Noel Menezes; Satyamurthy Pullela; Florentin Dartu; Lawrence T. Pillage (ICCAD, 1994)

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. - Jessica Qian; Satyamurthy Pullela; Lawrence T. Pillage (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. - Noel Menezes; Satyamurthy Pullela; Lawrence T. Pileggi (DAC, 1995)

Post-processing of clock trees via wiresizing and buffering for robust design. - Satyamurthy Pullela; Noel Menezes; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Library-less synthesis for static CMOS combinational logic circuits. - Sergey Gavrilov; Alexey Glebov; Satyamurthy Pullela; S. C. Moore; Abhijit Dharchoudhury; Rajendran Panda; Gopalakrishnan Vijayan; David T. Blaauw (ICCAD, 1997)

Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. - Abhijit Dharchoudhury; David T. Blaauw; Joe Norton; Satyamurthy Pullela; J. Dunning (ICCD, 1997)

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. - Satyamurthy Pullela; Noel Menezes; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Clock Distribution Methodology for PowerPCTM Microprocessors. - Shantanu Ganguly; Daksh Lehther; Satyamurthy Pullela (J. VLSI Signal Process., 1997)

CMOS Combinational Circuit Sizing by Stage-wise Tapering. - Satyamurthy Pullela; Rajendran Panda; Abhijit Dharchoudhury; Gopal Vija (DATE, 1998)