Analyzing static and dynamic write margin for nanometer SRAMs. - Jiajing Wang; Satyanand Nalam; Benton H. Calhoun (ISLPED, 2008)

Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T. - Satyanand Nalam; Benton H. Calhoun (CICC, 2009)

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. - Satyanand Nalam; Mudit Bhargava; Kyle Ringgenberg; Ken Mai; Benton H. Calhoun (ICCD, 2009)

Improving SRAM Vmin and yield by using variation-aware BTI stress. - Jiajing Wang; Satyanand Nalam; Zhenyu Qi 001; Randy W. Mann; Mircea R. Stan; Benton H. Calhoun (CICC, 2010)

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. - Satyanand Nalam; Mudit Bhargava; Ken Mai; Benton H. Calhoun (DAC, 2010)

Limits of bias based assist methods in nano-scale 6T SRAM. - Randy W. Mann; Satyanand Nalam; Jiajing Wang; Benton H. Calhoun (ISQED, 2010)

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. - Satyanand Nalam; Vikas Chandra; Cezary Pietrzyk; Robert C. Aitken; Benton H. Calhoun (ISQED, 2010)

Dynamic write limited minimum operating voltage for nanoscale SRAMs. - Satyanand Nalam; Vikas Chandra; Robert C. Aitken; Benton H. Calhoun (DATE, 2011)

5T SRAM With Asymmetric Sizing for Improved Read Stability. - Satyanand Nalam; Benton H. Calhoun (IEEE J. Solid State Circuits, 2011)

Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories. - Sudhanshu Khanna; Satyanand Nalam; Benton H. Calhoun (VLSID, 2014)

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2015)

17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. - John Keane 001; Jaydeep Kulkarni; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (ISSCC, 2016)

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Xiaofei Wang; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2016)

5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. - Jaydeep P. Kulkarni; John Keane 001; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2017)

A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. - Zheng Guo; Daeyeon Kim; Satyanand Nalam; Jami Wiedemer; Xiaofei Wang; Eric Karl (ISSCC, 2018)

A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications. - Zheng Guo; Daeyeon Kim; Satyanand Nalam; Jami Wiedemer; Xiaofei Wang; Eric Karl (IEEE J. Solid State Circuits, 2019)