VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. - Saurabh Kotiyal; Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (CSC, 2005)

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. - Himanshu Thapliyal; Saurabh Kotiyal; M. B. Srinivas (VLSI Design, 2006)

Mach-Zehnder interferometer based design of all optical reversible binary adder. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (DATE, 2012)

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (ISVLSI, 2012)

Design of Testable Reversible Sequential Circuits. - Himanshu Thapliyal; Nagarajan Ranganathan; Saurabh Kotiyal (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (VLSID, 2014)

Efficient reversible NOR gates and their mapping in optical computing domain. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (Microelectron. J., 2014)

Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (Trans. Comput. Sci., 2014)

Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. - Himanshu Thapliyal; Nagarajan Ranganathan; Saurabh Kotiyal (Field-Coupled Nanocomputing, 2014)

Reversible logic based multiplication computing unit using binary tree data structure. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (J. Supercomput., 2015)

Design Methodologies for Reversible Logic Based Barrel Shifters. - Saurabh Kotiyal; Himanshu Thapliyal (J. Circuits Syst. Comput., 2016)