Scaling of iDDT Test Methods for Random Logic Circuits. - Ali Chehab; Saurabh Patel; Rafic Z. Makki (J. Electron. Test., 2006)

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. - Samuel Leshner; Krzysztof S. Berezowski; Xiaoyin Yao; Gayathri Chalivendra; Saurabh Patel; Sarma B. K. Vrudhula (ISVLSI, 2010)

Multimodal Sentiment Analysis: Perceived vs Induced Sentiments. - Aditi Aggarwal; Deepika Varshney; Saurabh Patel (CoRR, 2023)